Intel E6420 Data Sheet - Page 96
Normal State, HALT and Extended HALT Powerdown States
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Features Figure 30. Processor Low Power State Machine Normal State - Normal Execution HALT or MWAIT Instruction and HALT Bus Cycle Generated INIT#, INTR, NMI, SMI#, RESET#, FSB interrupts Extended HALT or HALT State - BCLK running - Snoops and interrupts allowed STPCLK# STPCLK# Asserted De-asserted Extended Stop Grant State or Stop Grant State - BCLK running - Snoops and interrupts allowed STPCLK# Asserted STPCLK# De-asserted Snoop Event Occurs Snoop Event Serviced Snoop Event Occurs Snoop Event Serviced Extended HALT Snoop or HALT Snoop State - BCLK running - Service Snoops to caches Extended Stop Grant Snoop or Stop Grant Snoop State - BCLK running - Service Snoops to caches 6.2.1 6.2.2 6.2.2.1 Normal State This is the normal operating state for the processor. HALT and Extended HALT Powerdown States The processor supports the HALT or Extended HALT powerdown state. The Extended HALT Powerdown must be enabled via the BIOS for the processor to remain within its specification. The Extended HALT state is a lower power state as compared to the Stop Grant State. If Extended HALT is not enabled, the default Powerdown state entered will be HALT. Refer to the following sections for details about the HALT and Extended HALT states. HALT Powerdown State HALT is a low power state entered when all the processor cores have executed the HALT or MWAIT instructions. When one of the processor cores executes the HALT instruction, that processor core is halted; however, the other processor continues normal operation. The processor transitions to the Normal state upon the occurrence of SMI#, INIT#, or LINT[1:0] (NMI, INTR). RESET# causes the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide for more information. 96 Datasheet