MSI P7N SLI-FI User Guide - Page 57

MS-7380 Mainboard, CAS LatencyCL, Memory Timings

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MS-7380 Mainboard CAS Latency(CL) W hen the Memory Timings sets to [Manual], the field is adjustable.This controls the CAS latency, which determines the timing delay (in clock cycles) before SDRAM starts a read command after receiving it. tRCD W hen the M emory Timings sets to [Manual], the field is adjustable. W hen DRAM is refreshed, both rows and columns are addressed separately. This setup item allows you to determine the timing of the transition from RAS (row address strobe) to CAS (column address strobe). The less the clock cycles, the faster the DRAM performance. tRP W hen the M emory Timings sets to [Manual], this field is adjustable. This setting controls the number of cycles for Row Address Strobe (RAS) to be allowed to precharge. If insufficient time is allowed for the RAS to accumulate its charge before DRAM refresh, refresh may be incomplete and DRAM may fail to retain data. This item applies only when synchronous DRAM is installed in the system. tRAS W hen the M emory Timings sets to [Manual], this field is adjustable. This setting determines the time RAS takes to read from and write to memory cell. tRRD W hen the Memory Timings sets to [Manual], the field is adjustable. Specifies the active-to-active delay of different banks. Time interval between a read and a precharge command. tRC W hen the Memory Timings sets to [Manual], the field is adjustable. The rowcycle time determines the minimum number of clock cycles a memory row takesto complete a full cycle, from row activation up to the precharging of the ac t i ver ow . tWR W hen the Memory Timings sets to [Manual], the field is adjustable. Minimum time interval between end of write data burst and the start of a precharge command. Allows sense amplifiers to restore data to cells. tWTR W hen the Memory Timings sets to [Manual], the field is adjustable. Minimum time interval between the end of write data burst and the start of a column-read command. It allows I/O gating to overdrive sense amplifiers before read command starts. tREF W hen the Memory Timings sets to [Manual], the field is adjustable. Specifies the refresh rate of the DIMM requiring the most frequent refresh. 3-20

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3-20
MS-7380 Mainboard
CAS Latency(CL)
When the
Memory Timings
sets to [Manual], the field is adjustable.This con-
trols the CAS latency, which determines the timing delay (in clock cycles) before
SDRAM starts a read command after receiving it.
tRCD
When the
Memory Timings
sets to [Manual], the field is adjustable. When
DRAM is refreshed, both rows and columns are addressed separately. This
setup item allows you to determine the timing of the transition from RAS (row
address strobe) to CAS (column address strobe). The less the clock cycles, the
faster the DRAM performance.
tRP
When the
Memory Timings
sets to [Manual], this field is adjustable. This
setting controls the number of cycles for Row Address Strobe (RAS) to be
allowed to precharge. If insufficient time is allowed for the RAS to accumulate its
charge before DRAM refresh, refresh may be incomplete and DRAM may fail to
retain data. This item applies only when synchronous DRAM is installed in the
system.
tRAS
When the
Memory Timings
sets to [Manual], this field is adjustable. This
setting determines the time RAS takes to read from and write to memory cell.
tRRD
When the
Memory Timings
sets to [Manual], the field is adjustable. Specifies
the active-to-active delay of different banks. Time interval between a read and
a precharge command.
tRC
When the
Memory Timings
sets to [Manual], the field is adjustable. The
rowcycle time determines the minimum number of clock cycles a memory row
takesto complete a full cycle, from row activation up to the precharging of the
activerow.
tWR
When the
Memory Timings
sets to [Manual], the field is adjustable. Minimum
time interval between end of write data burst and the start of a precharge
command. Allows sense amplifiers to restore data to cells.
tWTR
When the
Memory Timings
sets to [Manual], the field is adjustable. Minimum
time interval between the end of write data burst and the start of a column-read
command. It allows I/O gating to overdrive sense amplifiers before read com-
mand starts.
tREF
When the
Memory Timings
sets to [Manual], the field is adjustable. Specifies
the refresh rate of the DIMM requiring the most frequent refresh.