Sony PCV-R556DS Reference Manual - Page 92

SDRAM Cycle Time Tras, Trc, Memory Hole At 15M-16M - uc

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78 VAIO Digital Studio™ Reference Manual Chip Configuration Sub-Menu SDRAM Configuration SDRAM CAS Latency SDRAM RAS to CAS Delay SDRAM RAS Precharge Time SDRAM Cycle Time (Tras, Trc) SDRAM Page Closing Policy CPU Latency Timer CPC Graphics Video Memory Cache Mode AGP 4X Support Memory Hole At 15M-16M PCI 2.1 Support High Priority PCI Mode Onboard PCI IDE Enable [By SPD] User Define 7ns (143MHz) 8ns (125MHz) [3T] [3T] [3T] [6T, 8T] 5T, 7T [All Banks] One Bank [Enabled] Disabled [Enabled] Disabled [64MB] 32MB [UC] USWC [Enabled] Disabled [Disabled] Enabled [Enabled] Disabled [Enabled] Disabled [Both] Primary Secondary Disabled

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VAIO Digital Studio
™
Reference Manual
78
Chip Configuration Sub-Menu
SDRAM Configuration
[By SPD]
User Define
7ns (143MHz)
8ns (125MHz)
SDRAM CAS Latency
[3T]
SDRAM RAS to CAS Delay
[3T]
SDRAM RAS Precharge Time
[3T]
SDRAM Cycle Time (Tras, Trc)
[6T, 8T]
5T, 7T
SDRAM Page Closing Policy
[All Banks]
One Bank
CPU Latency Timer
[Enabled]
Disabled
CPC
[Enabled]
Disabled
Graphics
[64MB]
32MB
Video Memory Cache Mode
[UC]
USWC
AGP 4X Support
[Enabled]
Disabled
Memory Hole At 15M-16M
[Disabled]
Enabled
PCI 2.1 Support
[Enabled]
Disabled
High Priority PCI Mode
[Enabled]
Disabled
Onboard PCI IDE Enable
[Both]
Primary
Secondary
Disabled