Toshiba 23HLV87 Circuit Diagrams - Page 24

Fe Regulator Schematic Diagram

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8 7 6 5 4 3 2 1 H-31 A B C D E F G FE REGULATOR SCHEMATIC DIAGRAM (DECODER PCB) EMC Close to XS001 DSPVCC33 DVDLD CDLD C205 NM [470pF] C216 NM [470pF] R221 10R + C312 47uF/16V + C315 100uF/16V 2 Q204 1298 3 1 R222 DSPVCC33 220R LD_DVD XS001 is used for Sanyo/Samsung/Sony OPUs R224 10R + C310 47uF/16V + C315 100uF/16V XS001 24Pin OPU connector C216 NC GND-LD DVD-LD NC HFM MD CD-LD VR-DVD VR-CD NC E VCC VC(VREF) GND/PD F B A RF CD/DVD_SW D C TT+ F+ F- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 OPU5V VC1 RF TACTTACT+ FACT+ FACT- C207 1nF C208 1nF C205 NC DVDLD Q205 1298 OPU_HFM CDLD VR_DVD VR_CD FB16 601 R217 33R C164 3 2 1 R223 220R LD_CD R202=300R, for HOP1200W only R202 0R [300R] C212 1nF RFA5V + C9 470uF/16V 2.1V 1nF RF_E VC RF_F RF_B RF_A RFP RF_D RF_C RFA5V R204 3.3K CD_DVD PDIC Control: DVD=LOW CD=HIGH CD_DVD 26 GND 25 GND C203 0.1uF C14 + C314 C11 + C13 0.1uF 0.1uF 10uF/16V 47uF/16V C165 33pF C152 C153 C157 NC NC NC C154 NC C155 NC C156 NC DSPVCC33 FOCUS_S SLED_S TRACK_S SPDL_S CLOSE OPEN DRVSB FOCUS_S SLED_S TRACK_S SPDL_S CLOSE OPEN DRVSB VC2 While using BA5954 OPU Sony310 DL3 IAT510 TOP1100S SEMCO-SP1 MITSM820W HD8(DV23) HOP1200W HD65/HD62 502W Arima681 R209 100R 0 100R 10R 0 91R 0 NM 0 91R NM R210 100R 0 100R 10R 0 91R 0 NM 0 91R NM OPU HOP1200W Arima681 Others R270 100R 100R NM R283 100R 100R NM While using AM5888s OPU R209 R210 R270 HD65 0 0R NM Hitachi NM NM 91R R283 NM 91R VR_CD R294 0R VR_DVD R295 0R OPU 313A HD62 R294: 100R 0R R295: 100R 0R 502W 91R 91R R210 0R [NM] MD_DVD MD_CD R209 0R [NM] R270 NM [91R] R283 NM [91R] 5VOUT Value in [ ] is for AM5888s FOCUS_S SLED_S FACT- VC2 DSPVCC33 R219 R R218 R R246 R280 R U202 AT5654 [BA5954/AM5888s] (value) is for AM5888s 1 VINFC STBY 28 C220 100pF 3V3_DRV 2 CFCERR1(TRB_1) BIAS 27 R255 47K 1V8_FB 3 CFCERR2(REGO2) VINTK 26 R229 0R VINSL+ 4 VINSL+ CTKERR1(TRB_2) 25 10K [NM] C223 R230 3V3_FB 22nF 6.8K 5 VINSL-(REGO1) 6 VOSL(FWD) CTKERR2(NC) 24 VINLD 23 7 VNFFC(REV) PREGND 22 TRACK_S 1V8_DRV C219 100pF [NM] R228 10K [NM] SPDL_S FB4 601 + C32 10uF/16V C245 0.1uF FACTFACT+ R267 SL_MOTSL_MOT+ 0R5 8 VCC 9 PVCC1(LOAD-) 10 PGND(LOAD+) 11 VOSL-(VOSL+) 12 VOSL+(VOSL-) 13 VOFC14 VOFC+ PVCC2 21 VNFTK(NC) 20 PGND(VCC2) 19 VOLD- 18 VOLD+ 17 VOTK- 16 VOTK+ 15 R225 0R5 [NM] R256 1K SP_MSP_MOT+ TACTTACT+ DRVSB 29 GND 30 GND1 HOMESW INSWIN R284 R285 NM [0R] 0R [NM] R254 4.7K C170 NM [1nF] C213 NM NC R236 4.7K C214 NM [1nF] C169 NM [1nF] R286 4.7K [NM] HOMESW IN_OUT_SW INSW C281 NM [1nF] C177 NM [1nF] HOMESW IN_OUT_SW INSW SP_MSL_MOT+ SL_MOTFACTFACT+ TACTTACT+ LOADLOAD+ 3V3_DRV 3V3_FB 1V8_DRV 1V8_FB 5VIN 5VOUT FB5 601 FB2 NC C15 NC XS2 PD2 1 LOAD- 2 LOAD+ 3 ACC 4 SP- 5 SP+ 6 SL+ 7 SL- 8 GND 9 LIMIT 10 PD1 11 TRYIN 12 ECR 13 5V 14 FG 15 STNBY 16 6P 2.0: SLED & SPINDLE Con 5VV 5VV 5VV R6 NM IN_OUT_SW Close to motor driver. DSPVCC33 DSPVCC18 R1 1K R2 10K D1 2 1298 1 [PSS8550] 3 R3 G-Y_OUT 4.7K 36966ⱘ199PIN LOADLOAD+ R205 NC SP_MOT+ SL_MOT+ SL_MOT- HOMESW INSWIN C12 0.1uF R7 R8 200 5VV 5VV 15K SPDL_PWM C16 27N 5VOUT DRVSB R13 0 VINSL+ SPDL_SENS- R14 NC R4 4.7K 5VV R9 1K C17 0.1uF R10 10K 1 2 D2 1298 [PSS8550] 3 R11 4.7K 5VV R12 4.7K 36966ⱘ200PIN R52 1K 1 3 R53 10K R54 4.7K D5 601 [NM] R264 1K 1% VC2 C242 0.1uF R265 1K 1% TRIN R278 33K C246 0.1uF BEMF Current Type(Default) SP_M- R281 1R R298 NC SPDL_SENSC162 NC SPDL_SENS- R206 R R245 NC DSPVCC18 SP_MOT- R207 R + C308 C160 10uF/16V 100N Voltage Type SP_MOT+ 3.4 R205 NM [3.3K] SP_MOT- 1.4 R206 NM [3.3K] R207 NM [220R] D205 NM [LL4148] 1 2 D206 D207 NM NM [LL4148] [LL4148] 1 2 SPDL_SENS+ [0.9, 3.3] SPDL_SENS- D208 NM [LL4148] 1 2 1 2 2 DSPVCC18 A B C D E F G H 8 7 6 5 4 3 2 1 H H-32

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2
1
3
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6
7
8
2
1
3
4
5
6
7
8
H-32
H-31
(DECODER PCB)
FE REGULATOR SCHEMATIC DIAGRAM
A
H
B
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5
1
C
C
N
3
5
1
C
C
N
1
2
3
5
D
1
0
6
]
M
N
[
5
D
1
0
6
]
M
N
[
5
4
2
C
F
u
1
.
0
5
4
2
C
F
u
1
.
0
4
1
2
C
M
N
]
F
n
1
[
4
1
2
C
M
N
]
F
n
1
[
1
2
7
0
2
D
M
N
]
8
4
1
4
L
L
[
7
0
2
D
M
N
]
8
4
1
4
L
L
[
2
6
1
C
C
N
2
6
1
C
C
N
0
7
2
R
M
N
]
R
1
9
[
0
7
2
R
M
N
]
R
1
9
[
F
p
0
0
1
0
2
2
C
F
p
0
0
1
0
2
2
C
8
0
2
C
F
n
1
8
0
2
C
F
n
1
0
0
2
7
R
0
0
2
7
R
6
5
1
C
C
N
6
5
1
C
C
N
3
5
R
K
0
1
3
5
R
K
0
1
2
1
2
C
F
n
1
2
1
2
C
F
n
1
5
B
F
1
0
6
5
B
F
1
0
6
1
2
3
4
0
2
Q
8
9
2
1
4
0
2
Q
8
9
2
1
+
2
3
C
V
6
1
/
F
u
0
1
+
2
3
C
V
6
1
/
F
u
0
1
+
2
1
3
C
V
6
1
/
F
u
7
4
+
2
1
3
C
V
6
1
/
F
u
7
4
9
6
1
C
M
N
]
F
n
1
[
9
6
1
C
M
N
]
F
n
1
[
1
8
2
C
M
N
]
F
n
1
[
1
8
2
C
M
N
]
F
n
1
[
5
6
2
R
%
1
K
1
5
6
2
R
%
1
K
1
1
2
8
0
2
D
M
N
]
8
4
1
4
L
L
[
8
0
2
D
M
N
]
8
4
1
4
L
L
[
K
7
.
4
3
R
K
7
.
4
3
R
F
p
0
0
1
9
1
2
C
]
M
N
[
F
p
0
0
1
9
1
2
C
]
M
N
[
4
6
2
R
%
1
K
1
4
6
2
R
%
1
K
1
3
0
2
C
F
u
1
.
0
3
0
2
C
F
u
1
.
0
R
8
1
2
R
R
8
1
2
R
R
0
8
2
R
R
0
8
2
R
5
0
2
C
M
N
]
F
p
0
7
4
[
5
0
2
C
M
N
]
F
p
0
7
4
[
M
N
4
8
2
R
]
R
0
[
M
N
4
8
2
R
]
R
0
[
2
1
C
F
u
1
.
0
2
1
C
F
u
1
.
0
3
8
2
R
M
N
]
R
1
9
[
3
8
2
R
M
N
]
R
1
9
[
2
R
K
0
1
2
R
K
0
1
7
0
2
R
R
7
0
2
R
R
K
7
4
5
5
2
R
K
7
4
5
5
2
R
6
4
2
C
F
u
1
.
0
6
4
2
C
F
u
1
.
0
D
L
-
D
N
G
4
2
D
L
-
D
V
D
3
2
C
N
2
2
M
F
H
1
2
D
M
0
2
D
L
-
D
C
9
1
D
V
D
-
R
V
8
1
D
C
-
R
V
7
1
C
N
6
1
E
5
1
C
C
V
4
1
)
F
E
R
V
(
C
V
3
1
D
P
/
D
N
G
2
1
F
1
1
B
0
1
A
9
F
R
8
W
S
_
D
V
D
/
D
C
7
D
6
C
5
-
T
4
+
T
3
+
F
2
-
F
1
GND
25
GND
26
1
0
0
S
X
r
o
t
c
e
n
n
o
c
U
P
O
n
i
P
4
2
1
0
0
S
X
r
o
t
c
e
n
n
o
c
U
P
O
n
i
P
4
2
K
7
.
4
4
5
R
K
7
.
4
4
5
R
6
8
2
R
K
7
.
4
]
M
N
[
6
8
2
R
K
7
.
4
]
M
N
[
4
0
2
R
K
3
.
3
4
0
2
R
K
3
.
3
M
N
5
0
2
R
]
K
3
.
3
[
M
N
5
0
2
R
]
K
3
.
3
[
2
B
F
C
N
2
B
F
C
N
5
9
2
R
R
0
5
9
2
R
R
0
K
0
1
8
2
2
R
]
M
N
[
K
0
1
8
2
2
R
]
M
N
[
2
5
1
C
C
N
2
5
1
C
C
N
8
R
K
5
1
8
R
K
5
1
+
5
1
3
C
V
6
1
/
F
u
0
0
1
+
5
1
3
C
V
6
1
/
F
u
0
0
1
K
1
1
R
K
1
1
R
4
B
F
1
0
6
4
B
F
1
0
6
6
1
2
C
C
N
6
1
2
C
C
N
9
0
2
R
R
0
]
M
N
[
9
0
2
R
R
0
]
M
N
[
1
2
3
5
0
2
Q
8
9
2
1
5
0
2
Q
8
9
2
1
2
4
2
C
F
u
1
.
0
2
4
2
C
F
u
1
.
0
6
3
2
R
K
7
.
4
6
3
2
R
K
7
.
4
F
n
1
4
6
1
C
F
n
1
4
6
1
C
5
R
0
5
2
2
R
]
M
N
[
5
R
0
5
2
2
R
]
M
N
[
+
3
1
C
V
6
1
/
F
u
0
1
+
3
1
C
V
6
1
/
F
u
0
1
4
R
K
7
.
4
4
R
K
7
.
4
4
2
2
R
R
0
1
4
2
2
R
R
0
1
1
2
2
R
R
0
1
1
2
2
R
R
0
1
6
1
C
N
7
2
6
1
C
N
7
2
1
2
3
1
D
8
9
2
1
]
0
5
5
8
S
S
P
[
1
D
8
9
2
1
]
0
5
5
8
S
S
P
[
K
0
1
6
4
2
R
]
M
N
[
K
0
1
6
4
2
R
]
M
N
[
1
0
6
6
1
B
F
1
0
6
6
1
B
F
+
5
1
3
C
V
6
1
/
F
u
0
0
1
+
5
1
3
C
V
6
1
/
F
u
0
0
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
9
8
7
6
5
4
3
2
1
2
S
X
n
o
C
E
L
D
N
I
P
S
&
D
E
L
S
:
0
.
2
P
6
2
S
X
n
o
C
E
L
D
N
I
P
S
&
D
E
L
S
:
0
.
2
P
6
5
R
0
7
6
2
R
5
R
0
7
6
2
R
+
0
1
3
C
V
6
1
/
F
u
7
4
+
0
1
3
C
V
6
1
/
F
u
7
4
1
8
2
R
R
1
1
8
2
R
R
1
7
5
1
C
C
N
7
5
1
C
C
N
0
1
2
R
R
0
]
M
N
[
0
1
2
R
R
0
]
M
N
[
4
9
2
R
R
0
4
9
2
R
R
0
5
0
2
C
C
N
5
0
2
C
C
N
6
1
2
C
M
N
]
F
p
0
7
4
[
6
1
2
C
M
N
]
F
p
0
7
4
[
M
N
6
0
2
R
]
K
3
.
3
[
M
N
6
0
2
R
]
K
3
.
3
[
K
1
9
R
K
1
9
R
5
0
2
R
C
N
5
0
2
R
C
N
6
0
2
R
R
6
0
2
R
R
5
1
C
C
N
5
1
C
C
N
4
5
2
R
K
7
.
4
4
5
2
R
K
7
.
4
2
0
2
R
R
0
]
R
0
0
3
[
2
0
2
R
R
0
]
R
0
0
3
[
1
1
R
K
7
.
4
1
1
R
K
7
.
4
3
1
R
0
3
1
R
0
8
9
2
R
C
N
8
9
2
R
C
N
R
0
5
8
2
R
]
M
N
[
R
0
5
8
2
R
]
M
N
[
4
5
1
C
C
N
4
5
1
C
C
N
1
2
3
2
D
8
9
2
1
]
0
5
5
8
S
S
P
[
2
D
8
9
2
1
]
0
5
5
8
S
S
P
[
+
9
C
V
6
1
/
F
u
0
7
4
+
9
C
V
6
1
/
F
u
0
7
4
+
8
0
3
C
V
6
1
/
F
u
0
1
+
8
0
3
C
V
6
1
/
F
u
0
1
7
1
C
F
u
1
.
0
7
1
C
F
u
1
.
0
5
6
1
C
F
p
3
3
5
6
1
C
F
p
3
3
R
0
9
2
2
R
R
0
9
2
2
R
K
8
.
6
0
3
2
R
K
8
.
6
0
3
2
R
R
0
2
2
3
2
2
R
R
0
2
2
3
2
2
R
1
2
5
0
2
D
M
N
]
8
4
1
4
L
L
[
5
0
2
D
M
N
]
8
4
1
4
L
L
[
7
7
1
C
M
N
]
F
n
1
[
7
7
1
C
M
N
]
F
n
1
[
R
0
2
2
2
2
2
R
R
0
2
2
2
2
2
R
R
9
1
2
R
R
9
1
2
R
K
1
2
5
R
K
1
2
5
R