Via EPIA-ML6000EAG User Manual - Page 58

Chapter 3 Frequency / Voltage Control Phoenix - AwardBIOS CMOS Setup Utility Frequency / Voltage Control DRAM Clock DRAM Timing SDRAM CAS Latency Bank Interleave Precharge to Active(Trp) Active to Precharge(Tras) Active to CMD(Trcd) REF to ACT/REF to REF(Trfc) ACT(0) to ACT(1) (TRRD) DRAM Command Rate [166 MHz] [Auto By SPD] 2.5 Disabled 4T 9T 4T 15T 3T [1T Command] Item Help Menu Level Spread Spectrum [Disabled] : Move Enter: Select F5: Previous Values +/-/PU/PD: Value F10: Save F6: Fail-Safe Defaults ESC: Exit F1: General F7: Optimized Defaults Help DRAM Clock The chipset supports synchronous and asynchronous mode between host clock and DRAM clock frequency. Settings: 66 MHz, 100 MHz, 133 MHz, and By SPD DRAM Timing The value in this field depends on the memory modules installed in your system. Changing the value from the factory setting is not recommended unless you install new memory that has a different performance rating than the original modules. Settings: Manual and By SPD SDRAM CAS Latency This item adjusts the speed it takes for the memory module to complete a command. Generally, a lower setting will improve the performance of your system. However, if your system becomes less stable, you should change it to a higher setting. This field is only available when DRAM Timing is set to Manual. Settings: 2, 2.5 3-26