Via EPIA-PX10000G User Manual - Page 50
PCI Master 0 WS Write, PCI Delay Transaction, DRDY_Timing
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Chapter 3 CPU & PCI BUS CONTROL PCI Master 0 WS Write PCI Delay Transaction DRDY_Timing Phoenix - AwardBIOS CMOS Setup Utility CPU & PCI Bus Control [Enabled] [Enabled] [Optimize] Item Help Menu Level : Move Enter: Select F5: Previous Values +/-/PU/PD: Value F10: Save F6: Fail-Safe Defaults ESC: Exit F1: General Help F7: Optimized Defaults PCI Master 0 WS Write Settings: [Enabled, Disabled] PCI Delay Transaction Settings: [Enabled, Disabled] DRDY_Timing Settings: [Slowest, Default, Optimize] 38
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Chapter 3
38
CPU
&
PCI
B
US
C
ONTROL
: Move
F5: Previous Values
F6: Fail-Safe Defaults
F7: Optimized Defaults
Enter: Select
+/-/PU/PD: Value
F10: Save
ESC: Exit
F1: General Help
Menu Level
Item Help
[Enabled]
PCI Master 0 WS Write
CPU & PCI Bus Control
Phoenix - AwardBIOS CMOS Setup Utility
PCI Delay Transaction
[Enabled]
DRDY_Timing
[Optimize]
PCI Master 0 WS Write
Settings: [Enabled, Disabled]
PCI Delay Transaction
Settings: [Enabled, Disabled]
DRDY_Timing
Settings: [Slowest, Default, Optimize]