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AMD AX1800DMT3C User Guide - Page 28

Exiting the Stop Grant State and Bus Connect Sequence, The Northbridge asserts CONNECT.

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Preliminary Information AMD Athlon™ XP Processor Model 6 Data Sheet 24309E-March 2002 Figure 5 shows the signal sequence of events that takes the processor out of the Stop Grant state, connects the processor to the AMD Athlon system bus, and puts the processor into the Working state. ST PCLK # PROCRDY CONNECT CLKFWDRST Figure 5. Exiting the Stop Grant State and Bus Connect Sequence The following sequence of events removes the processor from the Stop Grant state and connects it to the system bus: 1. The Southbridge deasserts STPCLK#, informing the processor of a wake event. 2. When the processor recognizes STPCLK# deassertion, it exits the low-power state and asserts PROCRDY, notifying the Northbridge to connect to the bus. 3. The Northbridge asserts CONNECT. 4. The Northbridge deasserts CLKFWDRST, synchronizing the forwarded clocks between the processor and the Northbridge. 5. The processor issues a Connect special cycle on the system bus and resumes operating system and application code execution. 16 Power Management Chapter 4

Section	Page
Contents	3
List of Figures	7
List of Tables	9
Revision History	11
1 Overview	13
1.1 QuantiSpeed™ Architecture Summary	14
2 Interface Signals	17
2.1 Overview	17
2.2 Signaling Technology	17
2.3 Push-Pull (PP) Drivers	18
2.4 AMD Athlon™ System Bus Signals	18
3 Logic Symbol Diagram	19
4 Power Management	21
4.1 Power Management States	21
Working State	22
Halt State	22
Stop Grant States	22
Probe State	24
4.2 Connect and Disconnect Protocol	25
Connect Protocol	25
Connect State Diagram	29
4.3 Clock Control	31
5 CPUID Support	33
6 Thermal Design	35
7 Electrical Data	37
7.1 Conventions	37
7.2 Interface Signal Groupings	37
7.3 Voltage Identification (VID[4:0])	38
7.4 Frequency Identification (FID[3:0])	39
7.5 VCCA AC and DC Characteristics	39
7.6 Decoupling	39
7.7 VCC_CORE Characteristics	40
7.8 Absolute Ratings	42
7.9 VCC_CORE Voltage and Current	43
7.10 SYSCLK and SYSCLK# AC and DC Characteristics	44
7.11 AMD Athlon™ System Bus AC and DC Characteristics	46
7.12 General AC and DC Characteristics	48
7.13 Open Drain Test Circuit	50
7.14 Thermal Diode Characteristics	51
7.15 APIC Pins AC and DC Characteristics	53
8 Signal and Power-Up Requirements	55
8.1 Power-Up Requirements	55
Signal Sequence and Timing Description	55
Clock Multiplier Selection (FID[3:0])	58
8.2 Processor Warm Reset Requirements	58
Northbridge Reset Pins	58
9 Mechanical Data	59
9.1 Introduction	59
9.2 Die Loading	59
9.3 OPGA Package Description	60
10 Pin Descriptions	63
10.1 Pin Diagram and Pin Name Abbreviations	63
10.2 Pin List	72
10.3 Detailed Pin Descriptions	80
A20M# Pin	80
AMD Pin	80
AMD Athlon™ System Bus Pins	80
Analog Pin	80
APIC Pins, PICCLK, PICD[1:0]#	80
CLKFWDRST Pin	80
CLKIN, RSTCLK (SYSCLK) Pins	80
CONNECT Pin	81
COREFB and COREFB# Pins	81
CPU_PRESENCE# Pin	81
DBRDY and DBREQ# Pins	81
FERR Pin	81
FID[3:0] Pins	82
FLUSH# Pin	83
IGNNE# Pin	83
INIT# Pin	83
INTR Pin	83
JTAG Pins	83
K7CLKOUT and K7CLKOUT# Pins	83
Key Pins	83
NC Pins	84
NMI Pin	84
PGA Orientation Pins	84
PLL Bypass and Test Pins	84
PWROK Pin	84
SADDIN[1:0]# and SADDOUT[1:0]# Pins	84
Scan Pins	84
SMI# Pin	85
STPCLK# Pin	85
SYSCLK and SYSCLK#	85
THERMDA and THERMDC Pins	85
VCCA Pin	85
VID[4:0] Pins	85
VREFSYS Pin	86
ZN and ZP Pins	86
11 Ordering Information	87
Appendix A	89