AMD AX1800DMT3C User Guide - Page 45

24309E-March 2002 Preliminary Information AMD Athlon™ XP Processor Model 6 Data Sheet Table 10 shows the SYSCLK/SYSCLK# differential clock AC characteristics of the AMD Athlon XP processor model 6. Table 10. SYSCLK and SYSCLK# AC Characteristics Symbol Parameter Description Minimum Maximum Units Notes Clock Frequency Duty Cycle 50 133 MHz 30% 70% t1 Period 7.5 ns 1, 2 t2 High Time 1.05 ns t3 Low Time 1.05 ns t4 Fall Time 2 ns t5 Rise Time 2 ns Period Stability ± 300 ps Notes: 1. Circuitry driving the AMD Athlon™ system bus clock inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the PLL to track the jitter. The -20dB attenuation point, as measured into a 10- or 20-pF load must be less than 500 kHz. 2. Circuitry driving the AMD Athlon system bus clock inputs may purposely alter the AMD Athlon system bus clock frequency (spread spectrum clock generators). In no cases can the AMD Athlon system bus period violate the minimum specification above. AMD Athlon system bus clock inputs can vary from 100% of the specified frequency to 99% of the specified frequency at a maximum rate of 100 kHz. Figure 10 shows a sample waveform of the SYSCLK signal. t2 VCROSS VThreshold-AC t3 t5 Figure 10. SYSCLK Waveform t4 t1 Chapter 7 Electrical Data 33