ASRock AB350M-HDV R3.0 User Manual - Page 56

AB350M-HDV R3.0 / A320M-HDV R3.0 / A320M-DVS R3.0 DRAM Timing Configuration DRAM Information Browse the serial presence defect (SPD) for DDR4 modules. DRAM Frequency If [Auto] is selected, the motherboard will detect the memory module(s) inserted and assign the appropriate frequency automatically. DRAM Timing Configuration Primary Timing CAS# Latency (tCL) The time between sending a column address to the memory and the beginning of the data in response. RAS# to CAS# Delay to Read (tRCDRD) RAS# to CAS# Delay : The number of clock cycles required between the opening of a row of memory and accessing columns within it. The number of clock cycles required between the opening of a row of memory and accessing columns within it RAS# to CAS# Delay to Write (tRCDWR) RAS# to CAS# Delay : The number of clock cycles required between the opening of a row of memory and accessing columns within it. The number of clock cycles required between the opening of a row of memory and accessing columns within it. Row Precharge Time (tRP) The number of clock cycles required between the issuing of the precharge command and opening the next row. RAS# Active Time (tRAS) The number of clock cycles required between a bank active command and issuing the precharge command. Secondary Timing Fail Count The number of training failure/retries required before boot from recovery mode. 51 English