ASRock AB350M-HDV R3.0 User Manual - Page 57

Write to Read Delay tWTR_L

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Refresh Cycle Time The Refresh command period. RAS to RAS Delay (tRRD_S) The number of clocks between two rows activated in different banks of the same rank. RAS to RAS Delay (tRRD_L) The number of clocks between two rows activated in different banks of the same rank. Four Activate Window (tFAW) The time window in which four activates are allowed the same rank. Write to Read Delay (tWTR_S) The number of clocks between the last valid write operation and the next read command to the same internal bank. Write to Read Delay (tWTR_L) The number of clocks between the last valid write operation and the next read command to the same internal bank. Write Recovery Time (tWR) The amount of delay that must elapse after the completion of a valid write operation, before an active bank can be precharged. Trcpage (tMAW,MAC) The minimum average time in memory clock cycles within a refresh window from an activate command to another activate command. TrdrdScL The minimum number of cycles from the last clock of virtual CAS of the first readburst operation to the clock in which CAS is asserted for a following read-burst operation in the same chipselect in the same bank group TwrwrScL The minimum number of cycles from the last clock of virtual CAS of a first writeburst operation to the clock in which CAS is asserted for a following write-burst operation in the same bank group. 52 English

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English
52
Refresh Cycle Time
°e Refresh command period.
RAS to RAS Delay (tRRD_S)
°e number of clocks between two rows activated in different banks of the same rank.
RAS to RAS Delay (tRRD_L)
°e number of clocks between two rows activated in different banks of the same
rank.
Four Activate Window (tFAW)
°e time window in which four activates are allowed the same rank.
Write to Read Delay (tWTR_S)
°e number of clocks between the last valid write operation and the next read command to
the same internal bank.
Write to Read Delay (tWTR_L)
°e number of clocks between the last valid write operation and the next read command to
the same internal bank.
Write Recovery Time (tWR)
°e amount of delay that must elapse aſter the completion of a valid write operation,
before an active bank can be precharged.
Trcpage (tMAW,MAC)
°e minimum average time in memory clock cycles within a refresh window from
an activate command to another activate command.
TrdrdScL
°e minimum number of cycles from the last clock of virtual CAS of the first read-
burst operation to the clock in which CAS is asserted for a following read-burst
operation in the same chipselect in the same bank group
TwrwrScL
°e minimum number of cycles from the last clock of virtual CAS of a first write-
burst operation to the clock in which CAS is asserted for a following write-burst
operation in the same bank group.