ASRock AB350M-HDV R3.0 User Manual - Page 58

Refresh Cycle Time tRFC, Refresh Cycle Time tRFC2, Refresh Cycle Time tRFC4, CAS Write Latency tCWL

Page 58 highlights

AB350M-HDV R3.0 / A320M-HDV R3.0 / A320M-DVS R3.0 Refresh Cycle Time (tRFC) The number of clocks from a Refresh command until the first Activate command to the same rank. Refresh Cycle Time (tRFC2) The number of clocks from a Refresh command until the first Activate command to the same rank. Refresh Cycle Time (tRFC4) The number of clocks from a Refresh command until the first Activate command to the same rank. CAS Write Latency (tCWL) Configure CAS Write Latency. Read to Precharge (tRTP) The number of clocks that are inserted between a read command to a row precharge command to the same rank. Trdwr The minimum number of cycles from the last clock of virtual CAS of the first readburst operation to the clock in which CAS is asserted for a following write-burst operation. Twrrd The minimum number of cycles from the last clock of virtual CAS of the first write-burst operation to the clock in which CAS is asserted for a following read-burst operation. TwrwrSc The minimum number of cycles from the last clock of virtual CAS of the first write-burst operation to the clock in which CAS is asserted for a following write-burst operation in the same chipselect. TwrwrSd The minimum number of cycles from the last clock of virtual CAS of the first write-burst operation to the clock in which CAS is asserted for a following write-burst operation in the same DIMM. 53 English

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AB350M-HDV R3.0 / A320M-HDV R3.0 / A320M-DVS R3.0
53
English
Refresh Cycle Time (tRFC)
°e number of clocks from a Refresh command until the first Activate command to
the same rank.
Refresh Cycle Time (tRFC2)
°e number of clocks from a Refresh command until the first Activate command to
the same rank.
Refresh Cycle Time (tRFC4)
°e number of clocks from a Refresh command until the first Activate command to
the same rank.
CAS Write Latency (tCWL)
Configure CAS Write Latency.
Read to Precharge (tRTP)
°e number of clocks that are inserted between a read command to a row pre-
charge command to the same rank.
Trdwr
°e minimum number of cycles from the last clock of virtual CAS of the first read-
burst operation to the clock in which CAS is asserted for a following write-burst
operation.
Twrrd
°e minimum number of cycles from the last clock of virtual CAS of the first write-burst
operation to the clock in which CAS is asserted for a following read-burst operation.
TwrwrSc
°e minimum number of cycles from the last clock of virtual CAS of the first write-burst
operation to the clock in which CAS is asserted for a following write-burst operation in the
same chipselect.
TwrwrSd
°e minimum number of cycles from the last clock of virtual CAS of the first write-burst
operation to the clock in which CAS is asserted for a following write-burst operation in the
same DIMM.