ASRock B365M Pro4 User Manual - Page 62

DRAM Timing Configuration, RAS# Active Time tRAS - xmp

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GT Frequency Configure the frequency of the integrated GPU. DRAM Configuration DRAM Tweaker Fine tune the DRAM settings by leaving marks in checkboxes. Click OK to confirm and apply your new settings. DRAM Timing Configuration Load XMP Setting Load XMP settings to overclock the memory and perform beyond standard specifications. DRAM Reference Clock Select Auto for optimized settings. DRAM Frequency If [Auto] is selected, the motherboard will detect the memory module(s) inserted and assign the appropriate frequency automatically. DRAM Clock Choose a frequency to override to clock delay for memory training. DRAM Clock controls memory training only if ASRock Timing Optimization is disabled. Primary Timing CAS# Latency (tCL) The time between sending a column address to the memory and the beginning of the data in response. RAS# to CAS# Delay and Row Precharge (tRCDtRP) RAS# to CAS# Delay : The number of clock cycles required between the opening of a row of memory and accessing columns within it. Row Precharge: The number of clock cycles required between the issuing of the precharge command and opening the next row. RAS# Active Time (tRAS) The number of clock cycles required between a bank active command and issuing the precharge command. 56 English

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56
English
GT Frequency
Configure the frequency of the integrated GPU.
DRAM Configuration
DRAM Tweaker
Fine tune the DRAM settings by leaving marks in checkboxes. Click OK to confirm and
apply your new settings.
DRAM Timing Configuration
Load XMP Setting
Load XMP settings to overclock the memory and perform beyond standard specifications.
DRAM Reference Clock
Select Auto for optimized settings.
DRAM Frequency
If [Auto] is selected, the motherboard will detect the memory module(s) inserted
and assign the appropriate frequency automatically.
DRAM Clock
Choose a frequency to override to clock delay for memory training. DRAM Clock
controls memory training only if ASRock Timing Optimization is disabled.
Primary Timing
CAS# Latency (tCL)
°e time between sending a column address to the memory and the beginning of the data
in response.
RAS# to CAS# Delay and Row Precharge (tRCDtRP)
RAS# to CAS# Delay : °e number of clock cycles required between the opening of a row
of memory and accessing columns within it.
Row Precharge: °e number of clock cycles required between the issuing of the precharge
command and opening the next row.
RAS# Active Time (tRAS)
°e number of clock cycles required between a bank active command and issuing the
precharge command.