ASRock Fatal1ty Z97 Killer/3.1 User Manual - Page 81

RAS to RAS Delay tRRD, Write to Read Delay tWTR

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Fatal1ty Z97 Killer/3.1 Series RAS# Active Time (tRAS) he number of clock cycles required between a bank active command and issuing the precharge command. Command Rate (CR) he delay between when a memory chip is selected and when the irst active command can be issued. Write Recovery Time (tWR) he amount of delay that must elapse ater the completion of a valid write operation, before an active bank can be precharged. Refresh Cycle Time (tRFC) he number of clocks from a Refresh command until the irst Activate command to the same rank. RAS to RAS Delay (tRRD) he number of clocks between two rows activated in diferent banks of the same rank. Write to Read Delay (tWTR) he number of clocks between the last valid write operation and the next read command to the same internal bank. Read to Precharge (tRTP) he number of clocks that are inserted between a read command to a row precharge command to the same rank. Four Activate Window (tFAW) he time window in which four activates are allowed the same rank. CAS Write Latency (tCWL) Conigure CAS Write Latency. tREFI Conigure refresh cycles at an average periodic interval. tCKE Conigure the period of time the DDR3 initiates a minimum of one refresh command internally once it enters Self-Refresh mode. 73 English

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Fatal1ty Z97 Killer/3.1 Series
73
English
RAS# Active Time (tRAS)
He number of clock cycles required between a bank active command and issuing the
precharge command.
Command Rate (CR)
He delay between when a memory chip is selected and when the ±rst active command can
be issued.
Write Recovery Time (tWR)
He amount of delay that must elapse a´er the completion of a valid write operation,
before an active bank can be precharged.
Refresh Cycle Time (tRFC)
He number of clocks from a Refresh command until the ±rst Activate command to
the same rank.
RAS to RAS Delay (tRRD)
He number of clocks between two rows activated in diµerent banks of the same
rank.
Write to Read Delay (tWTR)
He number of clocks between the last valid write operation and the next read
command to the same internal bank.
Read to Precharge (tRTP)
He number of clocks that are inserted between a read command to a row pre-
charge command to the same rank.
Four Activate Window (tFAW)
He time window in which four activates are allowed the same rank.
CAS Write Latency (tCWL)
Con±gure CAS Write Latency.
tREFI
Con±gure refresh cycles at an average periodic interval.
tCKE
Con±gure the period of time the DDR3 initiates a minimum of one refresh
command internally once it enters Self-Refresh mode.