ASRock H610M-HDV/M.2 R2.0 User Manual - Page 53
Write to Read Delay tWTR_S
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rank. RAS to RAS Delay (tRRD_S) The number of clocks between two rows activated in different banks of the same rank. Write to Read Delay (tWTR_L) The number of clocks between the last valid write operation and the next read command to the same internal bank. Write to Read Delay (tWTR_S) The number of clocks between the last valid write operation and the next read command to the same internal bank. Read to Precharge (tRTP) The number of clocks that are inserted between a read command to a row precharge command to the same rank. Four Activate Window (tFAW) The time window in which four activates are allowed the same rank. CAS Write Latency (tCWL) Configure CAS Write Latency. Third Timing tREFI Configure refresh cycles at an average periodic interval. tCKE Configure the period of time the DDR4 initiates a minimum of one refresh command internally once it enters Self-Refresh mode. tRC Use this item to change RAS# Cycle Time (tRC) Auto/Manual setting. Turn Around Timing Turn Around Timing Optimization Auto is enabled in general case. TAT Training Value 46 English