ASRock H81M-HDS R2.0 User Manual - Page 54

Write to Read Delay tWTR, RAS to RAS Delay tRRD

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Refresh Cycle Time (tRFC) he number of clocks from a Refresh command until the irst Activate command to the same rank. RAS to RAS Delay (tRRD) he number of clocks between two rows activated in diferent banks of the same rank. Write to Read Delay (tWTR) he number of clocks between the last valid write operation and the next read command to the same internal bank. Read to Precharge (tRTP) he number of clocks that are inserted between a read command to a row precharge command to the same rank. Four Activate Window (tFAW) he time window in which four activates are allowed the same rank. CAS Write Latency (tCWL) Conigure CAS Write Latency. tREFI Conigure refresh cycles at an average periodic interval. tCKE Conigure the period of time the DDR3 initiates a minimum of one refresh command internally once it enters Self-Refresh mode. tRDRD Conigure between module read to read delay. tRDRDDR Conigure between module read to read delay from diferent ranks. tRDRDDD Use this to change DRAM tRWSR Auto/Manual settings. he default is [Auto]. tWRRD Conigure between module write to read delay. 50 English

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English
Refresh Cycle Time (tRFC)
He number of clocks from a Refresh command until the ±rst Activate command to
the same rank.
RAS to RAS Delay (tRRD)
He number of clocks between two rows activated in diµerent banks of the same
rank.
Write to Read Delay (tWTR)
He number of clocks between the last valid write operation and the next read
command to the same internal bank.
Read to Precharge (tRTP)
He number of clocks that are inserted between a read command to a row pre-
charge command to the same rank.
Four Activate Window (tFAW)
He time window in which four activates are allowed the same rank.
CAS Write Latency (tCWL)
Con±gure CAS Write Latency.
tREFI
Con±gure refresh cycles at an average periodic interval.
tCKE
Con±gure the period of time the DDR3 initiates a minimum of one refresh
command internally once it enters Self-Refresh mode.
tRDRD
Con±gure between module read to read delay.
tRDRDDR
Con±gure between module read to read delay from diµerent ranks.
tRDRDDD
Use this to change DRAM tRWSR Auto/Manual settings. He default is [Auto].
tWRRD
Con±gure between module write to read delay.