ASRock H81M-HDS R2.0 User Manual - Page 55

Twrrddr, Rtl Cha, Io-l Cha, Odt Wr Cha

Get ASRock H81M-HDS R2.0 PDF manuals and user guides View all ASRock H81M-HDS R2.0 manuals
Add to My Manuals
Save this manual to your list of manuals

Page 55 highlights

H81M-HDS R2.0 tWRRDDR Conigure between module write to read delay from diferent ranks. tWRRDDD Use this to change DRAM tRRSR Auto/Manual settings. he default is [Auto]. Conigure between module write to read delay from diferent DIMMs. tWRWR Conigure between module write to write delay. tWRWRDR Conigure between module write to write delay from diferent ranks. tWRWRDD Conigure between module write to write delay from diferent DIMMs. tRDWR Conigure between module read to write delay. tRDWRDR Conigure between module read to write delay from diferent ranks. tRDWRDD Conigure between module read to write delay from diferent DIMMs. RTL (CHA) Conigure round trip latency for channel A. RTL (CHB) Conigure round trip latency for channel B. IO-L (CHA) Conigure IO latency for channel A. IO-L (CHB) Conigure IO latency for channel B. ODT WR (CHA) Conigure the memory on die termination resistors' WR for channel A. 51 English

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
H81M-HDS R2.0
51
English
tWRRDDR
Con±gure between module write to read delay from diµerent ranks.
tWRRDDD
Use this to change DRAM tRRSR Auto/Manual settings. He default is [Auto].
Con±gure between module write to read delay from diµerent DIMMs.
tWRWR
Con±gure between module write to write delay.
tWRWRDR
Con±gure between module write to write delay from diµerent ranks.
tWRWRDD
Con±gure between module write to write delay from diµerent DIMMs.
tRDWR
Con±gure between module read to write delay.
tRDWRDR
Con±gure between module read to write delay from diµerent ranks.
tRDWRDD
Con±gure between module read to write delay from diµerent DIMMs.
RTL (CHA)
Con±gure round trip latency for channel A.
RTL (CHB)
Con±gure round trip latency for channel B.
IO-L (CHA)
Con±gure IO latency for channel A.
IO-L (CHB)
Con±gure IO latency for channel B.
ODT WR (CHA)
Con±gure the memory on die termination resistors' WR for channel A.