ASRock X99 OC Formula/3.1 User Manual - Page 82

RAS# Active Time tRAS

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DRAM Boot Voltage Use this to conigure DRAM Boot Voltage. he default value is [Auto]. DRAM Eventual Voltage Use this to conigure the eventual voltages of the DIMM slots. he default value is [Auto]. DRAM Reference Clock Select Auto for optimized settings. DRAM Frequency If [Auto] is selected, the motherboard will detect the memory module(s) inserted and assign the appropriate frequency automatically. DRAM Frequency OC Preset If the DRAM frequency is selected, the corresponding DRAM and BCLK frequency for overclocking will be set. Primary Timing CAS# Latency (tCL) he time between sending a column address to the memory and the beginning of the data in response. RAS# to CAS# Delay (tRCD) he number of clock cycles required between the opening of a row of memory and accessing columns within it. Row Precharge Time (tRP) he number of clock cycles required between the issuing of the precharge command and opening the next row. RAS# Active Time (tRAS) he number of clock cycles required between a bank active command and issuing the precharge command. Command Rate (CR) he delay between when a memory chip is selected and when the irst active command can be issued. 76 English

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76
English
DRAM Boot Voltage
Use this to con±gure DRAM Boot Voltage. He default value is [Auto].
DRAM Eventual Voltage
Use this to con±gure the eventual voltages of the DIMM slots. He default value is [Auto].
DRAM Reference Clock
Select Auto for optimized settings.
DRAM Frequency
If [Auto] is selected, the motherboard will detect the memory module(s) inserted
and assign the appropriate frequency automatically.
DRAM Frequency OC Preset
If the DRAM frequency is selected, the corresponding DRAM and BCLK frequency for
overclocking will be set.
Primary Timing
CAS# Latency (tCL)
He time between sending a column address to the memory and the beginning of the data
in response.
RAS# to CAS# Delay (tRCD)
He number of clock cycles required between the opening of a row of memory and
accessing columns within it.
Row Precharge Time (tRP)
He number of clock cycles required between the issuing of the precharge command
and opening the next row.
RAS# Active Time (tRAS)
He number of clock cycles required between a bank active command and issuing the
precharge command.
Command Rate (CR)
He delay between when a memory chip is selected and when the ±rst active command can
be issued.