ASRock Z390 Extreme4 User Manual - Page 71

IOL Offset CH B

Page 71 highlights

Z390 Extreme4 RTL (CH A) Configure round trip latency for channel A. RTL (CH B) Configure round trip latency for channel B. IO-L (CH A) Configure IO latency for channel A. IO-L (CH B) Configure IO latency for channel B. IOL Offset (CH A) Configure IO latency offset for channel A. IOL Offset (CH B) Configure IO latency offset for channel B. RFR Delay (CH A) Configure RFR Delay for Channel A. RFR Delay (CH B) Configure RFR Delay for Channel B. ODT Setting ODT WR (A1) Configure the memory on die termination resistors' WR for channel A1. ODT WR (A2) Configure the memory on die termination resistors' WR for channel A2. ODT WR (B1) Configure the memory on die termination resistors' WR for channel B1. ODT WR (B2) Configure the memory on die termination resistors' WR for channel B2. ODT NOM (A1) Use this to change ODT (CH A1) Auto/Manual settings. The default is [Auto]. 65 English

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English
65
Z390 Extreme4
RTL (CH A)
Configure round trip latency for channel A.
RTL (CH B)
Configure round trip latency for channel B.
IO-L (CH A)
Configure IO latency for channel A.
IO-L (CH B)
Configure IO latency for channel B.
IOL Offset (CH A)
Configure IO latency offset for channel A.
IOL Offset (CH B)
Configure IO latency offset for channel B.
RFR Delay (CH A)
Configure RFR Delay for Channel A.
RFR Delay (CH B)
Configure RFR Delay for Channel B.
ODT Setting
ODT WR (A1)
Configure the memory on die termination resistors' WR for channel A1.
ODT WR (A2)
Configure the memory on die termination resistors' WR for channel A2.
ODT WR (B1)
Configure the memory on die termination resistors' WR for channel B1.
ODT WR (B2)
Configure the memory on die termination resistors' WR for channel B2.
ODT NOM (A1)
Use this to change ODT (CH A1) Auto/Manual settings. °e default is [Auto].