ASRock Z390 Extreme4 User Manual - Page 73

Clock Slew Rate, MRS tCCD_L

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Z390 Extreme4 Control Driving Adjust Control Driving for better signal. Default is 20. Clock Driving Adjust Clock Driving for better signal. Default is 26. DQ Slew Rate Adjust DQ Slew Rate for better signal. Default is 59. Command Slew Rate Adjust Command Slew Rate for better signal. Default is 53 for IN, 89 for 2N. Contorl Slew Rate Adjust Control Slew Rate for better signal. Default is 53. Clock Slew Rate Adjust Clock Slew Rate for better signal. Default is 53. MRS Setting MRS tCL Configure the tCL for Memory MRS MR0. MRS tWRtRTP Configure the tWRtRTP for Memory MRS MRC. MRS tCWL Configure the tCWL for Memory MRS MR2. MRS tCCD_L Configure the tCL for Memory MRS MR6. Advanced Setting ASRock Timing Optimization Configure the fast path through the MRC. Realtime Memory Timing Configure the realtime memory timings. [Enabled] The system will allow performing realtime memory timing changes after MRC_DONE. 67 English

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English
67
Z390 Extreme4
Control Driving
Adjust Control Driving for better signal. Default is 20.
Clock Driving
Adjust Clock Driving for better signal. Default is 26.
DQ Slew Rate
Adjust DQ Slew Rate for better signal. Default is 59.
Command Slew Rate
Adjust Command Slew Rate for better signal. Default is 53 for IN, 89 for 2N.
Contorl Slew Rate
Adjust Control Slew Rate for better signal. Default is 53.
Clock Slew Rate
Adjust Clock Slew Rate for better signal. Default is 53.
MRS Setting
MRS tCL
Configure the tCL for Memory MRS MR0.
MRS tWRtRTP
Configure the tWRtRTP for Memory MRS MRC.
MRS tCWL
Configure the tCWL for Memory MRS MR2.
MRS tCCD_L
Configure the tCL for Memory MRS MR6.
Advanced Setting
ASRock Timing Optimization
Configure the fast path through the MRC.
Realtime Memory Timing
Configure the realtime memory timings.
[Enabled]
°e system will allow performing realtime memory timing changes aſter
MRC_DONE.