ASRock Z690M PG Riptide/D5 User Manual - Page 70
RAS to RAS Delay tRRD_L
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BCLK Frequency Configure the BCLK Frequency. Primary Timing CAS# Latency (tCL) The time between sending a column address to the memory and the beginning of the data in response. RAS# to CAS# Delay (tRCD) The number of clock cycles required between the opening of a row of memory and accessing columns within it. Row Precharge (tRP) The number of clock cycles required between the issuing of the precharge command and opening the next row. RAS# Active Time (tRAS) The number of clock cycles required between a bank active command and issuing the precharge command. Command Rate (CR) The delay between when a memory chip is selected and when the first active command can be issued. Secondary Timing Write Recovery Time (tWR) The amount of delay that must elapse after the completion of a valid write operation, before an active bank can be precharged. Refresh Cycle Time 2 (tRFC2) The number of clocks from a Refresh command until the first Activate command to the same rank. Refresh Cycle Time per Bank (tRFCpb) The number of clocks that a per back Refresh command takes to complete. RAS to RAS Delay (tRRD_L) The number of clocks between two rows activated in different banks of the same rank. 62 English