Asus KCMR-D12 User Guide - Page 83

Hyper Transport Configuration

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Lane Reversal [Disabled] Configuration options: [Disabled] [Enabled] NB-SB Port Features NB-SB Link ASPM [L1] Configuration options: [Disabled] [L1] NP NB-SB VC1 Traffic Support [Disabled] Configuration options: [Disabled] [Enabled] Compliance Mode [Disabled] Configuration options: [Disabled] [Enabled] PCIE Slot 2/4 Core Setting; PCIE Slot 5 Core Setting; PIKE Slot/PCIE Slot 7 Core Setting Powerdown Unused lanes [Enabled] Configuration options: [Disabled] [Enabled] Turn Off PLL During L1/L23 [Enabled] Configuration options: [Disabled] [Enabled] TX Drive Strength [Auto] Configuration options: [Auto] [26mA] [20mA] [22mA] [24mA] TXCLK Clock Gating in L1 [Enabled] Configuration options: [Disabled] [Enabled] LCLK Clock Gating in L1 [Enabled] Configuration options: [Disabled] [Enabled] SB Core Setting TX Drive Strength [Auto] Configuration options: [Auto] [26mA] [20mA] [22mA] [24mA] TXCLK Clock Gating in L1 [Enabled] Configuration options: [Disabled] [Enabled] LCLK Clock Gating in L1 [Enabled] Configuration options: [Disabled] [Enabled] Hyper Transport Configuration HT Extended Address [Disabled] Configuration options: [Auto] [Disabled] [Enabled] HT3 Link Power State [Auto] Configuration options: [Auto] [LS0] [LS1] [LS2] [LS3] UnitID Clumping [Auto] Configuration options: [Auto] [Disabled] [UnitID 2/3] [UnitID B/C] [UnitID 2/3&B/C] ASUS KCMR-D12 4-25

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ASUS KCMR-D12
4-25
Lane Reversal [Disabled]
Configuration options: [Disabled] [Enabled]
NB-SB Port Features
NB-SB Link ASPM [L1]
Configuration options: [Disabled] [L1]
NP NB-SB VC1 Traffic Support [Disabled]
Configuration options: [Disabled] [Enabled]
Compliance Mode [Disabled]
Configuration options: [Disabled] [Enabled]
PCIE Slot 2/4 Core Setting; PCIE Slot 5 Core Setting;
PIKE Slot/PCIE Slot 7 Core Setting
Powerdown Unused lanes [Enabled]
Configuration options: [Disabled] [Enabled]
Turn Off PLL During L1/L23 [Enabled]
Configuration options: [Disabled] [Enabled]
TX Drive Strength [Auto]
Configuration options: [Auto] [26mA] [20mA] [22mA] [24mA]
TXCLK Clock Gating in L1 [Enabled]
Configuration options: [Disabled] [Enabled]
LCLK Clock Gating in L1 [Enabled]
Configuration options: [Disabled] [Enabled]
SB Core Setting
TX Drive Strength [Auto]
Configuration options: [Auto] [26mA] [20mA] [22mA] [24mA]
TXCLK Clock Gating in L1 [Enabled]
Configuration options: [Disabled] [Enabled]
LCLK Clock Gating in L1 [Enabled]
Configuration options: [Disabled] [Enabled]
Hyper Transport Configuration
HT Extended Address [Disabled]
Configuration options: [Auto] [Disabled] [Enabled]
HT3 Link Power State [Auto]
Configuration options: [Auto] [LS0] [LS1] [LS2] [LS3]
UnitID Clumping [Auto]
Configuration options: [Auto] [Disabled] [UnitID 2/3] [UnitID B/C]
[UnitID 2/3&B/C]