Asus P5GD1 P5GD1 User's Manual English Version E1673 - Page 82
Hyper-Threading Technology [Enabled], Advanced Chipset Settings, Con DRAM Timing by SPD [
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Hyper-Threading Technology [Enabled] Allows you to enable or disable the processor Hyper-Threading Technology. Configuration options: [Disabled] [Enabled] 4.4.5 Chipset The Chipset menu allows you to change the advanced chipset settings. Select an item then press to display the sub-menu. Advanced Chipset Settings Configure DRAM Timing by SPD [Enabled] Booting Graphic Adapter Priori [PCI Express/PCI] PEG Buffer Length PCI-EX Ports Configuration VC1 for Azalia & Root Ports [Auto] [Disabled] Sl tS Advanced Chipset Settings Configure DRAM Timing by SPD [Enabled] When this item is enabled, the DRAM timing parameters are set according to the DRAM SPD (Serial Presence Detect). When disabled, you can manually set the DRAM timing parameters through the DRAM sub-items. The following sub-items appear when this item is Disabled. Configuration options: [Disabled] [Enabled] DRAM CAS# Latency [5 Clocks] Controls the latency between the SDRAM read command and the time the data actually becomes available. Configuration options: [5 Clocks] [4 Clocks] DRAM RAS# Precharge [4 Clocks] Controls the idle clocks after issuing a precharge command to the DDR SDRAM. Configuration options: [2 Clocks] [3 Clocks] [4 Clocks] [5 Clocks] DRAM RAS# to CAS# Delay [4 Clocks] Controls the latency between the DDR SDRAM active command and the read/write command. Configuration options: [2 Clocks] [3 Clocks] [4 Clocks] [5 Clocks] DRAM RAS# Activate to Precharge Delay [15 Clocks] Configuration options: [4 Clocks] [5 Clocks] ~ [15 Clocks] 4-24 Chapter 4: BIOS setup