Asus PRIME A620-PLUS WIFI PRIME PROART TUF GAMING AMD AM5 Series BIOS Manual E - Page 35

Prefetcher settings, Core Watchdog, Platform First Error Handling, Opcache Control, Streaming Stores

Page 35 highlights

Prefetcher settings L1 Stream HW Prefetcher Allows you to enable or disable L1 Stream HW Prefetcher. Configuration options: [Disable] [Enable] [Auto] L2 Stream HW Prefetcher Allows you to enable or disable L2 Stream HW Prefetcher. Configuration options: [Disable] [Enable] [Auto] L1 Stride Prefetcher Uses memory access history of individual instructions to fetch additional lines when each access is a constant distance from the previous. Configuration options: [Disable] [Enable] [Auto] L1 Region Prefetcher Uses memory access history to fetch additional lines when the data access for a given instruction tends to be followed by other data accesses. Configuration options: [Disable] [Enable] [Auto] L2 Up/Down Prefetcher Uses memory access history to determine whether to fetch the next or previous line for all memory accesses. Configuration options: [Disable] [Enable] [Auto] Core Watchdog Core Watchdog Timer Enable Allows you to enable or disable CPU Watchdog Timer. Configuration options: [Disabled] [Enabled] [Auto] The following items appear only when Core Watchdog Timer Enable is set to [Enabled]. Core Watchdog Timer Interval Allows you to select CPU Watchdog Timer interval. Configuration options: [Auto] [39.68us] [80.64us] [162.56us] [326.4us] [654.08us] [1.309ms] [2.620ms] [5.241ms] [10.484ms] [20.970ms] [40.64ms] [82.53ms] [166.37ms] [334.05ms] [669.41ms] [1.340s] [2.681s] [5.364s] [10.730s] [21.461s] Core Watchdog Timer Severity Allows you to specify the CPU Watchdog Time severity (MSRC001_0074[CpuWdTmrCfgSeverity]). Configuration options: [No Error] [Transparent] [Corrected] [Deferred] [Uncorrected] [Fatal] [Auto] Platform First Error Handling Allows you to enable or disable PFEH, cloack individual banks, and mask deferred error interrupts from each bank. Configuration options: [Enabled] [Disabled] [Auto] Opcache Control Allows you to enable or disable the Opcache. Configuration options: [Disabled] [Enabled] [Auto] Streaming Stores Control Allows you to enable or disable the Streaming Stores functionality. Configuration options: [Disabled] [Enabled] [Auto] PRIME / ProArt / TUF GAMING AMD 600 Series BIOS Manual 35

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94

PRIME / ProArt / TUF GAMING AMD 600 Series BIOS Manual
35
Prefetcher settings
L1 Stream HW Prefetcher
Allows you to enable or disable L1 Stream HW Prefetcher.
Configuration options: [Disable] [Enable] [Auto]
L2 Stream HW Prefetcher
Allows you to enable or disable L2 Stream HW Prefetcher.
Configuration options: [Disable] [Enable] [Auto]
L1 Stride Prefetcher
Uses memory access history of individual instructions to fetch additional lines when each
access is a constant distance from the previous.
Configuration options: [Disable] [Enable] [Auto]
L1 Region Prefetcher
Uses memory access history to fetch additional lines when the data access for a given
instruction tends to be followed by other data accesses.
Configuration options: [Disable] [Enable] [Auto]
L2 Up/Down Prefetcher
Uses memory access history to determine whether to fetch the next or previous line for
all memory accesses.
Configuration options: [Disable] [Enable] [Auto]
Core Watchdog
Core Watchdog Timer Enable
Allows you to enable or disable CPU Watchdog Timer.
Configuration options: [Disabled] [Enabled] [Auto]
The following items appear only when
Core Watchdog Timer Enable
is set to
[Enabled]
.
Core Watchdog Timer Interval
Allows you to select CPU Watchdog Timer interval.
Configuration options: [Auto] [39.68us] [80.64us] [162.56us] [326.4us] [654.08us]
[1.309ms] [2.620ms] [5.241ms] [10.484ms] [20.970ms] [40.64ms] [82.53ms] [166.37ms]
[334.05ms] [669.41ms] [1.340s] [2.681s] [5.364s] [10.730s] [21.461s]
Core Watchdog Timer Severity
Allows you to specify the CPU Watchdog Time severity
(MSRC001_0074[CpuWdTmrCfgSeverity]).
Configuration options: [No Error] [Transparent] [Corrected] [Deferred] [Uncorrected]
[Fatal] [Auto]
Platform First Error Handling
Allows you to enable or disable PFEH, cloack individual banks, and mask deferred
error interrupts from each bank.
Configuration options: [Enabled] [Disabled] [Auto]
Opcache Control
Allows you to enable or disable the Opcache.
Configuration options: [Disabled] [Enabled] [Auto]
Streaming Stores Control
Allows you to enable or disable the Streaming Stores functionality.
Configuration options: [Disabled] [Enabled] [Auto]