Asus Z9NR-D12 User Guide - Page 43

Q-Code table Action Normal boot PHASE POST CODE Security Phase 01 02 03 06 04 PEI(Pre-EFI 10 initialization) phase 15 19 78~00 A1 A3 A7 A8 A9 AA AB AC AD AE AF 2F B0 B1 AF B4 B2 B3 B5 B6 B7 B8 B9 BA BB BC BF 5A 31 32 34 36 4F TYPE Progress Progress Progress Progress Progress Progress Progress Progress Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress Progress Progress Progress Progress Progress DESCRIPTION First post code(POWER_ON_POST_CODE) Load BSP microcode(MICROCODE_POST_CODE) Set cache as ram for PEI phase(CACHE_ENABLED_POST_CODE) CPU Early init.(CPU_EARLY_INIT_POST_CODE) initializes South bridge for PEI preparation PEI Core Entry NB initialize before installed memory SB initialize before installed memory Wait BMC ready(duration: 120 seconds). QPI initialization QPI initialization QPI initialization QPI initialization QPI initialization QPI initialization QPI initialization QPI initialization QPI initialization QPI initialization QPI initialization Complete Memory Init. Memory Init. Memory Init. RC Reset if require Memory Init. Memory Init. Memory Init. Memory Init. Memory Init. Memory Init. Memory Init. Memory Init. Memory Init. Memory Init. Memory Init. Memory Init. Done Other config. After RC end Memory already installed. CPU Init. CPU Init. CPU Init. DXE Initial Program Load(IPL) (continued on the next page) ASUS Z9NR-D12 2-23