Dell PowerEdge M710HD Technical Guide - Page 22

Dell 7 Memory 7.1 Overview The Dell™ PowerEdge™ M710HD uses DDR3 memory providing a high performance, high-speed memory interface capable of low latency response and high throughput. The PowerEdge M710HD supports registered ECC DDR3 DIMMs (RDIMM) as well as the low-voltage RDIMMs. The DDR3 memory interface consists of three channels, with up to three RDIMMs per channel for single/dual rank, and up to two RDIMMs per channel for quad rank. The interface uses 2 GB, 4 GB, 8 GB, or 16GB RDIMMs. The memory mode is dependent on how the memory is populated in the system as detailed below: • Three channels per processor populated identically: o Typically, the system will be set to run in Memory Optimized (Independent Channel) mode in this configuration. This mode offers the most DIMM population flexibility and system memory capacity, but offers the least number of RAS (reliability, availability, service) features. o All three channels must be populated identically. o Memory sparing is supported on M710HD. o Memory sparing requires that all the DIMMs are identically populated in all three channels. One channel will be the spare and not accessible as system memory until brought online to replace a failing channel. • The first two channels per processor populated identically with the third channel unused: o Typically, two channels operate in Advanced ECC (Lockstep) mode with each other by having the cache line split across both channels. This mode provides improved RAS features (SDDC support for x8-based memory). o For Memory Mirroring, two channels operate as mirrors of each other-writes go to both channels and reads alternate between the two channels. • One channel per processor populated: o This is a simple Memory Optimized mode. No mirroring or sparing is supported. o Low Voltage DIMMs will run at the lower voltage for configurations with one or two DIMMs per channel. o Three DIMM per channel configuration of low-voltage DIMMs will run at normal power consumption. The PowerEdge M710HD memory interface supports memory demand and patrol scrubbing, single-bit correction and multi-bit error detection. Correction of a x4 or x8 device failure is also possible with SDDC in the Advanced ECC mode. Additionally, correction of an x4 device failure is possible in the Memory Optimized mode. • If DIMMs of different speeds are mixed, all channels will operate at the fastest common frequency. • If memory mirroring is enabled, identical DIMMs must be installed in the same slots across both channels. The third channel of each processor is unavailable for memory mirroring. • The first DIMM slot in each channel is color-coded with white ejection tabs for ease of installation. • The DIMM sockets are placed 380 mils (11.43 mm) or 400 mils apart, center-to-center. PowerEdge M710HD Technical Guide 22