Dell PowerEdge M710HD Technical Guide - Page 25

Chipset

Page 25 highlights

Dell 8 Chipset 8.1 Overview The Dell™ PowerEdge™ M710HD planar incorporates the Intel® 5520 chipset for I/O and processor interfacing which was designed to support Intel Xeon® Processor 5500 and 5600 series, QuickPath Interconnect, and PCIe Gen2. 8.2 I/O Hub The M710HD system board uses the Intel 5520 chipset 36D I/O Hub (IOH) to provide a link between the processor(s) and I/O components. The main components of the IOH consist of two full-width QuickPath Interconnect links (one to each processor), 36 lanes of PCIe Gen2, and a x4 Direct Media Interface (DMI) and an integrated IOxAPIC. 8.3 QuickPath Interconnect The QuickPath Interconnect (QPI) architecture consists of serial point-to-point interconnects for the processors and the IOH. The M710HD has a total of three QPI links: one link connecting the processors and links connecting both processors with the IOH. Each link consists of 20 lanes (full-width) in each direction with a link speed maximum of 6.4 GT/s. An additional lane is reserved for a forwarded clock. Data is sent over the QPI links as packets. The QuickPath Architecture implemented in the IOH and processors features four layers. The physical layer consists of the actual connection between components. It supports Polarity Inversion and Lane Reversal for optimizing component placement and routing. The Link layer is responsible for flow control and the reliable transmission of data. The Routing layer is responsible for the routing of QPI data packets. Finally, the Protocol layer is responsible for high-level protocol communications, including the implementation of a MESIF (Modify, Exclusive, Shared, Invalid, Forward) cache coherence protocol. 8.4 IOH PCIe PCIe is a serial point-to-point interconnect for I/O devices. PCIe Gen2 doubles the signaling bit rate of Gen1 from 2.5 Gb/s to 5 Gb/s. Each of the PCIe Gen2 ports are backwards-compatible with Gen1 transfer rates. The M710HD uses the Intel 5520 chipset 36D IOH that has one ESI port (port 0) as well as two PCIe Gen2 ports (ports 1,2) and 8 PCIe x4 ports (ports 3-10). Certain adjacent x4 ports can be combined into x8 ports (ports 7-8 and 9-10) the Network Daughter Card ports can also be combined into an x8 port as well The M710HD blade planers have a dedicated connector for the Network Daughter Card (NDC). Physically, a PCIe -2 x8 connection is routed from IOH to the NDC connector. This connection is dedicated to the M710HD LOM solution. See Table 8. PowerEdge M710HD Technical Guide 25

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Dell
PowerEdge M710HD Technical Guide
25
8
Chipset
8.1
Overview
The Dell
P
owerEdge™
M710HD planar incorporates the Intel
®
5520 chipset for I/O and processor
interfacing which was designed to support Intel Xeon
®
Processor 5500 and 5600 series, QuickPath
Interconnect, and PCIe Gen2.
8.2
I/O Hub
The M710HD system board uses the Intel 5520 chipset 36D I/O Hub (IOH) to provide a link between
the processor(s) and I/O components. The main components of the IOH consist of two full-width
QuickPath Interconnect links (one to each processor), 36 lanes of PCIe Gen2, and a x4 Direct Media
Interface (DMI) and an integrated IOxAPIC.
8.3
QuickPath Interconnect
The QuickPath Interconnect (QPI) architecture consists of serial point-to-point interconnects for the
processors and the IOH. The M710HD has a total of three QPI links: one link connecting the processors
and links connecting both processors with the IOH. Each link consists of 20 lanes (full-width) in each
direction with a link speed maximum of 6.4 GT/s. An additional lane is reserved for a forwarded
clock. Data is sent over the QPI links as packets.
The QuickPath Architecture implemented in the IOH and processors features four layers. The physical
layer consists of the actual connection between components. It supports Polarity Inversion and Lane
Reversal for optimizing component placement and routing. The Link layer is responsible for flow
control and the reliable transmission of data. The Routing layer is responsible for the routing of QPI
data packets. Finally, the Protocol layer is responsible for high-level protocol communications,
including the implementation of a MESIF (Modify, Exclusive, Shared, Invalid, Forward) cache
coherence protocol.
8.4
IOH PCIe
PCIe is a serial point-to-point interconnect for I/O devices. PCIe Gen2 doubles the signaling bit rate
of Gen1 from 2.5 Gb/s to 5 Gb/s. Each of the PCIe Gen2 ports are backwards-compatible with Gen1
transfer rates.
The M710HD uses the Intel 5520 chipset 36D IOH that has one ESI port (port 0) as well as two PCIe
Gen2 ports (ports 1,2) and 8 PCIe x4 ports (ports 3-10). Certain adjacent x4 ports can be combined
into x8 ports (ports 7-8 and 9-10) the Network Daughter Card ports can also be combined into an x8
port as well
The M710HD blade planers have a dedicated connector for the Network Daughter Card (NDC).
Physically, a PCIe -2 x8 connection is routed from IOH to the NDC connector. This connection is
dedicated to the M710HD LOM solution. See Table 8.