Epson Apex 386/33 Canadian Product User Manual - Page 142
Technical Information, The Intel 80386 Microprocessor, Cache Algorithm
View all Epson Apex 386/33 Canadian Product manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 142 highlights
6-4 Technical Information The Intel 80386 Microprocessor Your mainboard uses an Intel 80386-33 microprocessor running at 33MHz. The Intel 80386 is a high-performance 32-bit microprocessor designed for multitasking operating systems. The processor can address up to 4 gigabytes of physical memory and 64 terabytes of virtual memory. It incorporates integrated memory management and protection in its architecture in the form of address-translation registers, advanced multitasking hardware, and a protect mechanism to support operating systems. In addition, its object code is compatible with the 8086 family of microprocessors. The 80386 has built-in features to support coprocessor-s, DMA and interrupts (both maskable and non-maskable). It has two modes of operation: Real Address mode and the Protected Virtual Address mode. In Real Address mode, the 80386 operates as a fast 8086 with a 32-bit extension if necessary. The Protected Virtual Address mode is the natural environment of the 80386. Software can perform a task switch into tasks designated as virtual 8086 mode tasks. Virtual 8086 tasks can be isolated and protected from one another by use of paging and l/O-permission bit mapping. Cache Algorithm In a cache memory system, all data are stored in main memory and some data are duplicated in the cache. When the processor accesses memory, it checks the cache first. If the desired data are in the fast-memory cache, the processor can access the data quickly. If the desired data are not in the cache, the data must be fetched from main memory. If the requested data are found in the cache, the memory access is called a cache hit; if not, it is called a cache miss. The hit rate is the percentage of accesses that are hits; it is affected by the size and physical organization of the cache, the cache algorithm, and the program being run. The following section describes the cache algorithm of your mainboard. Chapter 6: Appendix 23