Foxconn A74MX-S English manual - Page 35
CPU Configuration
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3 CPU Configuration CMOS Setup Utility - Copyright (C) 1985-2006, American Megatrends, Inc. CPU Configuration �C��P��U��C��o�n��fi�g�u�r�a��ti�o�n Help Item Module Version : 13.28 AGESA Version : 3.1.7.0 Enable/disable the Physical Count : 1 generation of ACPI Logical Count : 2 _PPC, _PSS, and _PCT objects. Revision : G2 �C��a�c�h�e��L�1�:��2�5�6��K�B �C��a�c�h�e��L�2 1�0�2�4��K�B� Cache L3 : N/A Current CPU Speed : 2200MHz Current CPU Multiplier : 11x Maximum FSB Multiplier : 11x Able to Change Frequency : Yes uCode Patch Level : None Required Cool 'N' Quiet [Enabled] C1E Support [Disabled]� �C�P��U�-N��B�H��T�L�i�n�k�S�p�e�e�d� [Auto] NCHT Incoming Link Width [Auto] Move Enter:Select +/-/:Value F10:Save ESC:Exit F1:General Help F9:Optimized Defaults This menu shows most of the CPU specifications. ► Cool 'N' Quiet (Appear only when CPU supports) This option helps lowering down the CPU frequency and voltage when system is idling. When the CPU speed is slowing down, the temperature will drop as well. ► C1E Support (Optional only if CPU supports) C1E represents Enhanced HALT State. It is a feature which CPU uses to reduce power consumption when in halt state. C1E drops the CPU's multiplier and voltage to lower levels when a HLT (halt) command is issued. This item is used to enable/disable the C1E support. ► CPU-NB HT Link Speed HT stands for HyperTransport bus. The CPUNB HT Speed option controls the physical speed of the CPU to Northbridge HT link using multipliers ranging x1 to x13. The physical speed of the link is determined by multiplying the CPU clock with the CPUNB HT Speed setting. ► NCHT Incoming Link Width / NCHT Outgoing Link Width The coherency refers to the caching of memory, and the HT links between processors are coherent HT links as the HT protocol includes messages for managing the cache protocol. Other (non processor-processor) HT links are Non-Coherent HT links, as they do not have memory cache. The HyperTransport link width and frequency are initialized between the adjacent coherent and/or noncoherent HyperTransport technology devices during the reset sequence. It is highly recommended to set to [Auto] for overall performance. 28