HP Evo D500 Comparison of Intel Pentium III and Pentium 4 Processor Performanc - Page 10

Pentium 4

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Comparison of Intel Pentium III and Pentium 4 Processor Performance White Paper 10 Pentium 4 Figure 5: Pentium 4 NetBurst Architecture Overview Again, the NetBurst micro-architecture attacks the frequency and IPC variables of the performance equation v‡uÃv‡†Ãhq‰hprqà ' €Ãhqà " ly €Ã†u‚…‡ after) silicon process technology, its redesigned architecture of the complete instruction pipeline, its execution engine, and its extension to the existing instruction set, which is as follows: • 20-Stage Pipeline as compared to a 10-stage Pipeline in the Pentium III - smaller workload per stage but at significantly faster execution time • Execution Trace Cache to remove the long latency associated with the instruction decoder from the main execution loop in the Pentium III • Rapid Execution Engine where multiple Arithmetic Logic Units (ALUs) are executed twice as fast as the core frequency, resulting in higher execution throughput, reduced execution latency, and extension of the total of execution ports to seven (7) as compared to five (5) in the Pentium III • Advanced Transfer Cache with much higher throughput at 54.4GB/s for a 1.7 GHz Xeon (32 bytes x one transfer per clock x 1.7 GHz) to feed the data-hungry execution units as compared to 16GB/s throughput at 1 GHz in the Pentium III

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Comparison of Intel Pentium III and Pentium 4 Processor Performance White Paper
10
Pentium 4
Figure 5: Pentium 4 NetBurst Architecture Overview
Again, the NetBurst micro-architecture attacks the frequency and IPC variables of the
performance equation
ly after) silicon process
technology, its redesigned architecture of the complete instruction pipeline, its execution engine,
and its extension to the existing instruction set, which is as follows:
•
20-Stage Pipeline as compared to a 10-stage Pipeline in the Pentium III
–
smaller workload
per stage but at significantly faster execution time
•
Execution Trace Cache to remove the long latency associated with the instruction decoder
from the main execution loop in the Pentium III
•
Rapid Execution Engine where multiple Arithmetic Logic Units (ALUs) are executed twice
as fast as the core frequency, resulting in higher execution throughput, reduced execution
latency, and extension of the total of execution ports to seven (7) as compared to five (5) in
the Pentium III
•
Advanced Transfer Cache with much higher throughput at 54.4GB/s for a 1.7 GHz Xeon (32
bytes x one transfer per clock x 1.7 GHz) to feed the data-hungry execution units as
compared to 16GB/s throughput at 1 GHz in the Pentium III