HP ML115 The AMD processor roadmap for industry-standard servers, 6th edition - Page 10

AMD Smart Fetch Technology, Enhanced AMD PowerNow! Technology, Independent Dynamic Core Technology

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AMD Smart Fetch Technology Smart Fetch Technology allows cores to enter a "halt" state during idle processing times, causing them to draw less power. Before entering the halt state, data from the L1 and L2 caches are transferred to the shared L3 cache so that the contents of the idle cores can be retrieved. Enhanced AMD PowerNow! Technology Native quad-core technology enables enhancements to AMD PowerNow! Technology across all four cores. Two power management enhancements-Independent Dynamic Core Technology and Dual Dynamic Power Management™-provide optimum performance-per-watt and power savings. Independent Dynamic Core Technology AMD's Independent Dynamic Core Technology allows each core to independently adjust its frequency to reduce power use based on application requirements (Figure 4). This enables more precise power management, which can reduce the total cost of ownership (TCO) of a data center. Figure 4. Independently controlled cores reduce power use. The voltage is locked to the core with the highest P-state. Dual Dynamic Power Management Dual Dynamic Power Management provides separate (split) power planes for the cores and memory controller. This can reduce idle power consumption and allow individual processors to be managed in multi-socket systems, thereby creating power-saving opportunities without compromising performance. Rapid Virtualization Indexing Rapid Virtualization Indexing is an innovation in AMD-V technology that reduces the overhead associated with software virtualization. With software virtualization, processor overhead increases as each guest OS and application vies for the host machine's physical resources; this results in decreased performance. Also, memory latency increases as the virtual machine monitor, or hypervisor, dynamically translates the memory addresses sent to and received from the memory controller. The hypervisor does this so that each guest application does not realize that it is being virtualized. The translation from virtual machine memory address to host machine physical address is achieved by using "shadow page tables" (Figure 5). 10

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AMD Smart Fetch Technology
Smart Fetch Technology allows cores to enter a "halt" state during idle processing times, causing
them to draw less power. Before entering the halt state, data from the L1 and L2 caches are
transferred to the shared L3 cache so that the contents of the idle cores can be retrieved.
Enhanced AMD PowerNow! Technology
Native quad-core technology enables enhancements to AMD PowerNow! Technology across all
four cores. Two power management enhancements—Independent Dynamic Core Technology and
Dual Dynamic Power Management™—provide optimum performance-per-watt and power savings.
Independent Dynamic Core Technology
AMD’s Independent Dynamic Core Technology allows each core to independently adjust its
frequency to reduce power use based on application requirements (Figure 4). This enables more
precise power management, which can reduce the total cost of ownership (TCO) of a data center.
Figure 4.
Independently controlled cores reduce power use. The voltage is locked to the core with the highest
P-state.
Dual Dynamic Power Management
Dual Dynamic Power Management provides separate (split) power planes for the cores and
memory controller. This can reduce idle power consumption and allow individual processors to be
managed in multi-socket systems, thereby creating power-saving opportunities without
compromising performance.
Rapid Virtualization Indexing
Rapid Virtualization Indexing is an innovation in AMD-V technology that reduces the overhead
associated with software virtualization. With software virtualization, processor overhead increases
as each guest OS and application vies for the host machine’s physical resources; this results in
decreased performance. Also, memory latency increases as the virtual machine monitor, or
hypervisor, dynamically translates the memory addresses sent to and received from the memory
controller. The hypervisor does this so that each guest application does not realize that it is being
virtualized. The translation from virtual machine memory address to host machine physical address
is achieved by using “shadow page tables” (Figure 5).
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