HP ML115 The AMD processor roadmap for industry-standard servers, 6th edition - Page 6

HyperTransport Technology HyperTransport is a point-to-point interconnect with two unidirectional links (see Figure 1) that directly connect the processors to each other and connect each processor to its dedicated memory banks, as well as to other I/O chipsets.4 Compared to a shared, parallel front-side bus, HyperTransport has the advantages of no overhead for bus arbitration and easier signal integrity maintenance, resulting in a scalable, high-bandwidth architecture. Each16-bit (2-byte) HyperTransport link is double-pumped, performing two data transfers per clock cycle. From HyperTransport 1.0 in 2001 to HyperTransport 3.0 in 2008, the maximum clock speed and transfer rate increased from 800 MHz (1.6 MT/s5) to a maximum of 2.4 GHz (4.8 GT/s) in each direction. This gives each HyperTransport 3.0 link a maximum data rate of 4.8 GT/s × 2 bytes per transfer, or 9.6 GB/s (19.2 GB/s aggregate data rate). Figure 1. The HyperTransport interconnect separates memory and I/O traffic and directly attaches memory to each processor, allowing memory capacity to scale with the number of processors. 4 HyperTransport Technology was invented at AMD with contributions from industry partners and is managed and licensed by the HyperTransport Technology Consortium, a Texas non-profit corporation. 5 MT/s, or megatransfers per second, equals the speed of the link in millions of cycles per second times the number of transfers per cycle. 6