HP ProLiant DL590/64 ProLiant DL590/64 Server Technology - Page 4
Maximum Performance and Innovative Technology, ProLiant DL590/64 Server Architecture
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TECHNOLOGY BRIEF (cont.) ECC - Error Checking and Correcting SDRAM - Synchronous Dynamic Random Access Memory PCI - Peripheral Component Interconnect TC020702TB ... MAXIMUM PERFORMANCE AND INNOVATIVE TECHNOLOGY The ProLiant DL590/64 server incorporates the new four-way Intel Itanium-based processors and larger ECC SDRAM configurations to deliver the maximum performance and availability required for Itanium-based applications in four-processor compute environments. Innovative ProLiant technology adds reliability, features such as redundant power distribution, and efficient system board and cooling designs. ProLiant DL590/64 Server Architecture The ProLiant DL590/64 server is Compaq's first Itanium-based product. The architecture (Figure 1) uses the Intel 82460GX chipset. The chipset includes a 133-megahertz (MHz) front-side bus that uses both edges of the clock cycle to produce 266 megatransfers per second and supports dual memory boards and up to four Intel Itanium processors. The ProLiant DL590/64 server architecture also includes support for up to 64 GB of industry-standard 100-MHz SDRAM and up to four PCI bridges with a total of 11 slots. Figure 1: Diagram of ProLiant DL590/64 server architecture. Processors The ProLiant DL590/64 server includes support for up to four 733-MHz or 800-MHz Itanium-based processors. The 733-MHz processors support a 2-megabyte (MB) Level 3 cache, while the 800-MHz processors support a 4-MB Level 3 cache. The IA-64 architecture enables greater parallelism than traditional architectures by combining static and dynamic scheduling, using speculative execution, and predicting code branches better than traditional architectures. To realize the performance improvements of this greater parallelism, the Itanium processor has additional hardware resources: 128 general-purpose integer registers, 128 floating point registers, 64 predicate registers, and many execution units with parallel instruction dispatch (which allows executing multiple instructions in parallel). 4
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