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Intel BLKD915PBLL Product Specification - Page 29

Channel 7.1 Audio Subsystem

UPC - 735858166447

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Product Description 1.9.3 8-Channel (7.1) Audio Subsystem The 8-channel (7.1) audio subsystem includes the following: • Intel 82801FR I/O Controller Hub (ICH6-R) • Realtek ALC880 audio codec • Microphone input that supports a single dynamic, condenser, or electret microphone The front and back panel audio connectors are configurable through the audio device drivers. The available configurable audio ports are shown in Figure 9. Front Panel Audio Connectors Line Out/ Retasking Jack F [Port 2] Mic In/ Retasking Jack A or E [Port 1] Surround Left and Right/ Retasking Jack H [Black] Center channel and LFE (Subwoofer)/ Retasking Jack G [Orange] Back Panel Audio Connectors Line In/Retasking Jack C [Blue] Line Out/Retasking Jack D [Lime Green] Mic In/Retasking Jack B [Pink] S/PDIF Digital Audio Out Coaxial S/PDIF Digital Audio Out Optical Figure 9. Front/Back Panel Audio Connector Options OM16993 29

Section	Page
Intel® Desktop Board D915PBL Technical Product Specification	1
Revision History / Disclaimer	2
Preface	3
Intended Audience	3
What This Document Contains	3
Typographical Conventions	3
Other Common Notation	4
Contents	5
1 Product Description	11
1.1 PCI Bus Terminology Change	11
1.2 Overview	12
1.2.1 Feature Summary	12
1.2.2 Manufacturing Options	13
1.2.3 Board Layout	14
1.2.4 Block Diagram	16
1.3 Online Support	17
1.4 Processor	17
1.5 System Memory	18
1.5.1 Memory Configurations	19
1.5.1.1 Dual Channel (Interleaved) Mode Configurations	20
1.5.1.2 Single Channel (Asymmetric) Mode Configurations	22
1.6 Intel® 915P Chipset	23
1.6.1 USB	23
1.6.2 IDE Support	23
1.6.2.1 Parallel ATE IDE Interface	23
1.6.2.2 Serial ATA Interfaces	24
1.6.2.3 Serial ATA RAID	25
1.6.2.4 RAID Boot Configuration Overview	25
1.6.2.5 SCSI Hard Drive Activity LED Connector (Optional)	25
1.6.3 Real-Time Clock, CMOS SRAM, and Battery	25
1.7 PCI Express Connectors	26
1.8 I/O Controller	26
1.8.1 Serial Ports	27
1.8.2 Parallel Port	27
1.8.3 Diskette Drive Controller	27
1.8.4 Keyboard and Mouse Interface	27
1.9 Audio Subsystem	28
1.9.1 Audio Subsystem Software	28
1.9.2 Audio Connectors	28
1.9.3 8-Channel (7.1) Audio Subsystem	29
1.10 LAN Subsystem	30
1.10.1 Intel® 82562EZ Physical Layer Interface Device	30
1.10.1.1 RJ-45 LAN Connector with Integrated LEDs	31
1.10.2 Alert Standard Format (ASF) Support	31
1.10.3 LAN Subsystem Software	32
1.10.4 Intel® Wireless Connect Technology (Optional)	32
1.11 Hardware Management Subsystem	32
1.11.1 Hardware Monitoring and Fan Control ASIC	32
1.11.2 Thermal Monitoring	33
1.11.3 Fan Monitoring	34
1.11.4 Chassis Intrusion and Detection	34
1.12 Power Management	34
1.12.1 ACPI	35
1.12.1.1 System States and Power States	36
1.12.1.2 Wake-up Devices and Events	37
1.12.2 Hardware Support	37
1.12.2.1 Power Connector	38
1.12.2.2 Fan Connectors	38
1.12.2.3 LAN Wake Capabilities	38
1.12.2.4 Instantly Available PC Technology	39
1.12.2.5 Resume on Ring	39
1.12.2.6 Wake from USB	39
1.12.2.7 Wake from PS/2 Devices	39
1.12.2.8 PME# Signal Wake-up Support	39
1.12.2.9 WAKE# Signal Wake-up Support	40
1.12.2.10 +5 V Standby Power Indicator LED	40
1.13 Trusted Platform Module (Optional)	41
1.13.1 System Requirements	41
1.13.2 Warning of Potential Data Loss	41
1.13.3 Security Precautions	42
1.13.3.1 Password Procedures	42
1.13.3.2 Emergency Recovery File Back Up Procedures	43
1.13.3.3 Hard Drive Image Backup Procedures	43
1.13.3.4 Clear Text Backup (Optional)	43
1.13.4 Trusted Platform Module Ownership	43
1.13.5 Enabling the Trusted Platform Module	44
1.13.6 Assuming Trusted Platform Module Ownership	44
1.13.7 Recovery Procedures	45
1.13.7.1 Recovering from Hard Disk Failure	45
1.13.7.2 Recovering from Desktop Board or TPM Failure	45
1.13.8 Clearing Trusted Platform Module Ownership	46
1.13.9 Software Support	47
2 Technical Reference	49
2.1 Introduction	49
2.2 Memory Resources	49
2.2.1 Addressable Memory	49
2.2.2 Memory Map	51
2.3 DMA Channels	51
2.4 Fixed I/O Map	52
2.5 PCI Configuration Space Map	53
2.6 Interrupts	54
2.7 PCI Conventional Interrupt Routing Map	55
2.8 Connectors	57
2.8.1 Back Panel Connectors	58
2.8.2 Component-side Connectors	60
2.8.2.1 Chassis Fan Connectors	63
2.8.2.2 Power Supply Connectors	64
2.8.2.3 Add-in Card Connectors	65
2.8.2.4 Auxiliary Front Panel Power/Sleep/ LED Connector	66
2.8.2.5 Front Panel Connector	66
2.8.2.5.1 Hard Drive Activity LED Connector [Yellow]	67
2.8.2.5.2 Reset Switch Connector [Purple]	67
2.8.2.5.3 Power/Sleep LED Connector [Green]	67
2.8.2.5.4 Power Switch Connector [Red]	67
2.8.2.6 Front Panel USB Connectors	67
2.8.2.7 Front Panel IEEE 1394a Connectors	68
2.9 Jumper Block	69
2.10 Mechanical Considerations	70
2.10.1 D915PBL Board Form Factor	70
2.10.2 I/O Shield	71
2.11 Electrical Considerations	72
2.11.1 DC Loading	72
2.11.2 Add-in Board Considerations	72
2.11.3 Fan Connector Current Capability	72
2.11.4 Power Supply Considerations	73
2.12 Thermal Considerations	74
2.13 Reliability	76
2.14 Environmental	77
2.15 Regulatory Compliance	78
2.15.1 Safety Regulations	78
2.15.2 EMC Regulations	78
2.15.2.1 FCC Compliance Statement (USA)	79
2.15.2.2 Canadian Compliance Statement	79
2.15.3 European Union Declaration of Conformity Statement	79
2.15.4 Product Ecology Statements	80
2.15.4.1 Disposal Considerations	80
2.15.4.2 Recycling Considerations	80
2.15.5 Product Certification Markings (Board Level)	81
3 Overview of BIOS Features	83
3.1 Introduction	83
3.2 BIOS Flash Memory Organization	84
3.3 Resource Configuration	84
3.3.1 PCI Autoconfiguration	84
3.3.2 PCI IDE Support	84
3.4 System Management BIOS (SMBIOS)	85
3.5 Legacy USB Support	85
3.6 BIOS Updates	86
3.6.1 Language Support	86
3.6.2 Custom Splash Screen	86
3.7 Boot Options	87
3.7.1 CD-ROM Boot	87
3.7.2 Network Boot	87
3.7.3 Booting Without Attached Devices	87
3.7.4 Changing the Default Boot Device During POST	87
3.8 Fast Booting Systems with Intel® Rapid BIOS Boot	88
3.8.1 Peripheral Selection and Configuration	88
3.8.2 Intel Rapid BIOS Boot	88
3.9 BIOS Security Features	89
4 Error Messages and Beep Codes	91
4.1 BIOS Error Messages	91
4.2 Port 80h POST Codes	93
4.3 Bus Initialization Checkpoints	97
4.4 Speaker	98