Intel DC53427HYE Technical Product Specification - Page 20

Memory Configurations - nuc support

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Intel NUC D53427RKE Technical Product Specification 1.4.1 Memory Configurations The processor supports the following types of memory organization: • Dual channel (Interleaved) mode. This mode offers the highest throughput for real world applications. Dual channel mode is enabled when the installed memory capacities of both SO-DIMM channels are equal. Technology and device width can vary from one channel to the other but the installed memory capacity for each channel must be equal. If different speed SO-DIMMs are used between channels, the slowest memory timing will be used. • Single channel (Asymmetric) mode. This mode is equivalent to single channel bandwidth operation for real world applications. This mode is used when only a single SO-DIMM is installed or the memory capacities are unequal. Technology and device width can vary from one channel to the other. If different speed SO-DIMMs are used between channels, the slowest memory timing will be used. For information about... Memory Configuration Examples Refer to: http://www.intel.com/support/motherboards/desktop/sb/cs011965.htm 20

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Intel NUC D53427RKE Technical Product Specification
20
1.4.1
Memory Configurations
The processor supports the following types of memory organization:
•
Dual channel (Interleaved) mode
.
This mode offers the highest throughput for
real world applications.
Dual channel mode is enabled when the installed memory
capacities of both SO-DIMM channels are equal.
Technology and device width can
vary from one channel to the other but the installed memory capacity for each
channel must be equal.
If different speed SO-DIMMs are used between channels,
the slowest memory timing will be used.
•
Single channel (Asymmetric) mode
.
This mode is equivalent to single channel
bandwidth operation for real world applications.
This mode is used when only a
single SO-DIMM is installed or the memory capacities are unequal.
Technology and
device width can vary from one channel to the other.
If different speed SO-DIMMs
are used between channels, the slowest memory timing will be used.
For information about…
Refer to:
Memory Configuration Examples
011965.htm