Intel E5310 Specification Update - Page 36

Interrupt) has been sent. Due to this erratum, this bit will not be set unless IA32_DEBUGCTL MSR (1D9H) bit [12] (which stops all Performance Monitor Counters upon a PMI) is also set. Implication: Unless IA32_DEBUGCTL[12] is set, IA32_PERF_GLOBAL_STATUS[62] will not indicate that a PMI was generated due to a PEBS Overflow. Workaround: It is possible for the software to set IA32_DEBUGCTL[12] to avoid this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AJ70. The BS Flag in DR6 May be Set for Non-Single-Step #DB Exception Problem: DR6 BS (Single Step, bit 14) flag may be incorrectly set when the TF (Trap Flag, bit 8) of the EFLAGS Register is set, and a #DB (Debug Exception) occurs due to one of the following: • DR7 GD (General Detect, bit 13) being bit set • INT1 instruction • Code breakpoint Implication: The BS flag may be incorrectly set for non-single-step #DB exception. Workaround: None identified Status: For the steppings affected, see the Summary Tables of Changes. AJ71. An Asynchronous MCE During a Far Transfer May Corrupt ESP Problem: If an asynchronous machine check occurs during an interrupt, call through gate, FAR RET or IRET and in the presence of certain internal conditions, ESP may be corrupted. Implication: If the MCE (Machine Check Exception) handler is called without a stack switch, then a triple fault will occur due to the corrupted stack pointer, resulting in a processor shutdown. If the MCE is called with a stack switch, e.g. when the CPL (Current Privilege Level) was changed or when going through an interrupt task gate, then the corrupted ESP will be saved on the new stack or in the TSS (Task State Segment), and will not be used. Workaround: Use an interrupt task gate for the machine check handler. Status: For the steppings affected, see the Summary Tables of Changes. AJ72. In Single-Stepping on Branches Mode, the BS Bit in the PendingDebug-Exceptions Field of the Guest State Area will be Incorrectly Set by VM-Exit on a MOV to CR8 Instruction Problem: In a system supporting Intel® Virtualization Technology, the BS bit (bit 14 of the Pending-Debug-Exceptions field) in the guest state area will be incorrectly set when all of the following conditions occur: • The processor is running in VMX non-root as a 64 bit mode guest • The "CR8-load existing" VM-execution control is 0 and the "use TPR shadow" VMexecution is 1 • Both BTF (Single-Step On Branches, bit 1) of the IA32_DEBUGCTL MSR (1D9H) Register and the TF (Trap Flag, bit 8) of the RFLAGS Register are set • "MOV CR8, reg" attempts to program a TPR (Task Priority Register) value that is below the TPR threshold and causes a VM-exit Implication: A Virtual-Machine will sample the BS bit and will incorrectly inject a Single-Step trap to the guest. Workaround: A Virtual-Machine Monitor must manually disregard the BS bit in the Guest State Area in case of a VM-exit due to a TPR value below the TPR threshold. Status: For the steppings affected, see the Summary Tables of Changes. 36 Intel® Xeon® Processor 5300 Series Specification Update, December 2010