Intel E5345 Data Sheet - Page 87

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

87

Thermal Specifications

be programmed from 12.5% on/ 87.5% off to 87.5% on/12.5% off in 12.5%

increments. On-Demand mode may be used in conjunction with the Thermal Monitor;

however, if the system tries to enable On-Demand mode at the same time the TCC is

engaged, the factory configured duty cycle of the TCC will override the duty cycle

selected by the On-Demand mode.

6.2.5

PROCHOT# Signal

An external signal, PROCHOT# (processor hot) is asserted when the processor die

temperature of any processor cores has reached its factory configured trip point. If

Thermal Monitor is enabled (note that Thermal Monitor must be enabled for the

processor to be operating within specification), the TCC will be active when PROCHOT#

is asserted. The processor can be configured to generate an interrupt upon the

assertion or de-assertion of PROCHOT#. Refer to the

Intel® 64 and IA-32 Architecture

Software Developer’s Manual

for specific register and programming details.

PROCHOT# is designed to assert at or a few degrees higher than maximum T

CASE

(as

specified by Thermal Profile A) when dissipating TDP power, and cannot be interpreted

as an indication of processor case temperature. This temperature delta accounts for

processor package, lifetime and manufacturing variations and attempts to ensure the

Thermal Control Circuit is not activated below maximum T

CASE

when dissipating TDP

power. There is no defined or fixed correlation between the PROCHOT# trip

temperature, or the case temperature. Thermal solutions must be designed to the

processor specifications and cannot be adjusted based on experimental measurements

of T

CASE

, or PROCHOT#.

6.2.6

FORCEPR# Signal

The FORCEPR# (force power reduction) input can be used by the platform to cause the

Quad-Core Intel® Xeon® Processor 5300 Series to activate the TCC. If the processor

supports Thermal Monitor 2 (TM2), and has Thermal Monitor 2 and Thermal Monitor

(TM) properly enabled, assertion of the FORCEPR# signal will immediately activate

Thermal Monitor 2. If the processor does not support Thermal Monitor 2, but has

Thermal Monitor properly enabled, FORCEPR# signal assertion will cause Thermal

Monitor to become active. Please refer to the

Quad-Core Intel® Xeon® Processor 5300

Series Specification Update

to determine which processors support TM2 and

Intel® 64

and IA-32 Architecture Software Developer’s Manual

for details on enabling these

capabilities. Assertion of the FORCEPR# signal will activate TCC for all processor cores.

The TCC will remain active until the system deasserts FORCEPR#.

FORCEPR# is an asynchronous input, which can be employed to thermally protect other

system components. To use the voltage regulator (VR) as an example, TCC circuit

activation will reduce the current consumption of the processor and the corresponding

temperature of the VR.

It should be noted that assertion of FORCEPR# does not automatically assert

PROCHOT#. As mentioned previously, the PROCHOT# signal is asserted when a high

temperature situation is detected. A minimum pulse width of 500

μ

s is recommended

when FORCEPR# is asserted by the system. Sustained activation of the FORCEPR#

signal may cause noticeable platform performance degradation.

Refer to the appropriate platform design guidelines for details on implementing the

FORCEPR# signal feature.

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	17
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	18
2.4.2 PLL Power Supply	19
2.5 Voltage Identification (VID)	19
2.6 Reserved, Unused, or Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	33
2.13.3 Die Voltage Validation	34
2.14 AGTL+ FSB Specifications	34
3 Mechanical Specifications	39
3.1 Package Mechanical Drawings	39
3.2 Processor Component Keepout Zones	43
3.3 Package Loading Specifications	43
3.4 Package Handling Guidelines	44
3.5 Package Insertion Specifications	44
3.6 Processor Mass Specifications	44
3.7 Processor Materials	44
3.8 Processor Markings	45
3.9 Processor Land Coordinates	45
4 Land Listing	49
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments	49
4.1.1 Land Listing by Land Name	49
4.1.2 Land Listing by Land Number	60
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	83
6.2 Processor Thermal Features	84
6.2.1 Thermal Monitor Features	84
6.2.2 Thermal Monitor (TM1)	84
6.2.3 Thermal Monitor 2	85
6.2.4 On-Demand Mode	86
6.2.5 PROCHOT# Signal	87
6.2.6 FORCEPR# Signal	87
6.2.7 THERMTRIP# Signal	88
6.3 Platform Environment Control Interface (PECI)	88
6.3.1 Introduction	88
6.3.2 PECI Specifications	89
7 Features	91
7.1 Power-On Configuration Options	91
7.2 Clock Control and Low Power States	91
7.2.1 Normal State	92
7.2.2 HALT or Extended HALT State	92
7.2.3 Stop-Grant State	94
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	94
7.3 Enhanced Intel SpeedStep® Technology	95
8 Boxed Processor Specifications	97
8.1 Introduction	97
8.2 Mechanical Specifications	99
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	99
8.2.2 Boxed Processor Heat Sink Weight	107
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	107
8.3 Electrical Requirements	107
8.3.1 Fan Power Supply (Active CEK)	107
8.3.2 Boxed Processor Cooling Requirements	108
8.4 Boxed Processor Contents	109
9 Debug Tools Specifications	111
9.1 Debug Port System Requirements	111
9.2 Target System Implementation	111
9.2.1 System Implementation	111
9.3 Logic Analyzer Interface (LAI)	111
9.3.1 Mechanical Considerations	112

Intel E5345 Data Sheet - Page 87

PROCHOT# Signal, 6.2.6 FORCEPR# Signal

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