Intel E5345 Data Sheet - Page 92

Features

92

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

of the lower processor power states. Refer to the applicable chipset specification and

the

Intel® 64 and IA-32 Architecture Software Developer’s Manual

for more

information.

7.2.1

Normal State

This is the normal operating state for the processor.

7.2.2

HALT or Extended HALT State

The Extended HALT state (C1E) is enabled via the BIOS. Refer to the

Intel® 64 and

IA-32 Architecture Software Developer’s Manual

.

The Extended HALT state must be

enabled for the processor to remain within its specifications.

The Extended HALT

state requires support for dynamic VID transitions in the platform.

7.2.2.1

HALT State

HALT is a low power state entered when the processor has executed the HALT or

MWAIT instruction. When one of the processor cores execute the HALT or MWAIT

instruction, that processor core is halted; however, the other processor continues

normal operation. The processor will transition to the Normal state upon the occurrence

of SMI#, BINIT#, INIT#, LINT[1:0] (NMI, INTR), or an interrupt delivered over the

front side bus. RESET# will cause the processor to immediately initialize itself.

The return from a System Management Interrupt (SMI) handler can be to either

Normal Mode or the HALT state. See the

Intel® 64 and IA-32 Intel® Architecture

Software Developer's Manual, Volume III: System Programming Guide

for more

information.

The system can generate a STPCLK# while the processor is in the HALT state. When the

system deasserts STPCLK#, the processor will return execution to the HALT state.

While in HALT state, the processor will process front side bus snoops and interrupts.

7.2.2.2

Extended HALT State

Extended HALT state is a low power state entered when all four processor cores have

executed the HALT or MWAIT instructions and Extended HALT state has been enabled

via the BIOS. When one of the processor cores executes the HALT instruction, that

processor core is halted; however, the other processor cores continue normal

operation. The Extended HALT state is a lower power state than the HALT state or Stop

Grant state. The Extended HALT state must be enabled for the processor to remain

within its specifications.

The processor will automatically transition to a lower core frequency and voltage

operating point before entering the Extended HALT state. Note that the processor FSB

frequency is not altered; only the internal core frequency is changed. When entering

the low power state, the processor will first switch to the lower bus to core frequency

ratio and then transition to the lower voltage (VID).

While in the Extended HALT state, the processor will process bus snoops.

Section	Page
1 Introduction	9
1.1 Terminology	11
1.2 State of Data	13
1.3 References	13
2 Electrical Specifications	15
2.1 Front Side Bus and GTLREF	15
2.2 Power and Ground Lands	16
2.3 Decoupling Guidelines	16
2.3.1 VCC Decoupling	16
2.3.2 VTT Decoupling	16
2.3.3 Front Side Bus AGTL+ Decoupling	17
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])	18
2.4.2 PLL Power Supply	19
2.5 Voltage Identification (VID)	19
2.6 Reserved, Unused, or Test Signals	21
2.7 Front Side Bus Signal Groups	22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals	24
2.9 Test Access Port (TAP) Connection	24
2.10 Platform Environmental Control Interface (PECI) DC Specifications	24
2.10.1 DC Characteristics	24
2.10.2 Input Device Hysteresis	25
2.11 Mixing Processors	26
2.12 Absolute Maximum and Minimum Ratings	26
2.13 Processor DC Specifications	27
2.13.1 Flexible Motherboard Guidelines (FMB)	27
2.13.2 VCC Overshoot Specification	33
2.13.3 Die Voltage Validation	34
2.14 AGTL+ FSB Specifications	34
3 Mechanical Specifications	39
3.1 Package Mechanical Drawings	39
3.2 Processor Component Keepout Zones	43
3.3 Package Loading Specifications	43
3.4 Package Handling Guidelines	44
3.5 Package Insertion Specifications	44
3.6 Processor Mass Specifications	44
3.7 Processor Materials	44
3.8 Processor Markings	45
3.9 Processor Land Coordinates	45
4 Land Listing	49
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments	49
4.1.1 Land Listing by Land Name	49
4.1.2 Land Listing by Land Number	60
5 Signal Definitions	71
5.1 Signal Definitions	71
6 Thermal Specifications	79
6.1 Package Thermal Specifications	79
6.1.1 Thermal Specifications	79
6.1.2 Thermal Metrology	83
6.2 Processor Thermal Features	84
6.2.1 Thermal Monitor Features	84
6.2.2 Thermal Monitor (TM1)	84
6.2.3 Thermal Monitor 2	85
6.2.4 On-Demand Mode	86
6.2.5 PROCHOT# Signal	87
6.2.6 FORCEPR# Signal	87
6.2.7 THERMTRIP# Signal	88
6.3 Platform Environment Control Interface (PECI)	88
6.3.1 Introduction	88
6.3.2 PECI Specifications	89
7 Features	91
7.1 Power-On Configuration Options	91
7.2 Clock Control and Low Power States	91
7.2.1 Normal State	92
7.2.2 HALT or Extended HALT State	92
7.2.3 Stop-Grant State	94
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	94
7.3 Enhanced Intel SpeedStep® Technology	95
8 Boxed Processor Specifications	97
8.1 Introduction	97
8.2 Mechanical Specifications	99
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)	99
8.2.2 Boxed Processor Heat Sink Weight	107
8.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)	107
8.3 Electrical Requirements	107
8.3.1 Fan Power Supply (Active CEK)	107
8.3.2 Boxed Processor Cooling Requirements	108
8.4 Boxed Processor Contents	109
9 Debug Tools Specifications	111
9.1 Debug Port System Requirements	111
9.2 Target System Implementation	111
9.2.1 System Implementation	111
9.3 Logic Analyzer Interface (LAI)	111
9.3.1 Mechanical Considerations	112

Intel E5345 Data Sheet - Page 92

Normal State, 7.2.2 HALT or Extended HALT State

Page 92 highlights