Intel E6420 Data Sheet - Page 77
Down VRD 11.0 Processor Power Delivery Design Guidelines
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Land Listing and Signal Descriptions Table 26. Signal Description (Sheet 1 of 9) Name Type Description THERMTRIP# TMS TRDY# TRST# VCC VCCPLL VCC_SENSE VCC_MB_ REGULATION VID[7:0] VID_SELECT Output Input In the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature approximately 20 °C above the maximum TC. Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond where permanent silicon damage may occur. Upon assertion of THERMTRIP#, the processor will shut off its internal clocks (thus, halting program execution) in an attempt to reduce the processor junction temperature. To protect the processor, its core voltage (VCC) must be removed following the assertion of THERMTRIP#. Driving of the THERMTRIP# signal is enabled within 10 μs of the assertion of PWRGOOD (provided VTT and VCC are valid) and is disabled on deassertion of PWRGOOD (if VTT or VCC are not valid, THERMTRIP# may also be disabled). Once activated, THERMTRIP# remains latched until PWRGOOD, VTT, or VCC is de-asserted. While the deassertion of the PWRGOOD, VTT, or VCC will de-assert THERMTRIP#, if the processor's junction temperature remains at or above the trip level, THERMTRIP# will again be asserted within 10 μs of the assertion of PWRGOOD (provided VTT and VCC are valid). TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. Input TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins/lands of all FSB agents. Input TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. Input VCC are the power pins for the processor. The voltage supplied to these pins is determined by the VID[7:0] pins. Input VCCPLL provides isolated power for internal processor FSB PLLs. VCC_SENSE is an isolated low impedance connection to processor Output core power (VCC). It can be used to sense or measure voltage near the silicon with little noise. Output This land is provided as a voltage regulator feedback sense point for VCC. It is connected internally in the processor package to the sense point land U27 as described in the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket. Output VID[7:0] (Voltage ID) signals are used to support automatic selection of power supply voltages (VCC). Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for more information. The voltage supply for these signals must be valid before the VR can supply VCC to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID signals becomes valid. The VID signals are needed to support the processor voltage specification variations. See Table 2 for definitions of these signals. The VR must supply the voltage that is requested by the signals, or disable itself. Output This land is tied high on the processor package and is used by the VR to choose the proper VID table. Refer to the Voltage RegulatorDown (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for more information. Datasheet 77