Intel E6600 Specification Update - Page 36

<= 0x10h May Cause FPU Instruction or Operand Pointer Corruption

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Errata Due to this erratum, a logical processor may not resume execution until the next targeted interrupt event or O/S timer tick following a locked store that spans across cache lines within the monitored address range. Implication: The logical processor that executed the MWAIT instruction may not resume execution until the next targeted interrupt event or O/S timer tick in the case where the monitored address is written by a locked store which is split across cache lines. Workaround: Do not use locked stores that span cache lines in the monitored address range. Status: For the steppings affected, see the Summary Tables of Changes. AI37. REP CMPS/SCAS Operations May Terminate Early in 64-bit Mode when RCX >= 0X100000000 Problem: REP CMPS (Compare String) and SCAS (Scan String) instructions in 64-bit mode may terminate before the count in RCX reaches zero if the initial value of RCX is greater than or equal to 0X100000000. Implication: Early termination of REP CMPS/SCAS operation may be observed and RFLAGS may be incorrectly updated. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AI38. Problem: FXSAVE/FXRSTOR Instructions which Store to the End of the Segment and Cause a Wrap to a Misaligned Base Address (Alignment

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Errata
36
Intel
®
Core™2 Extreme Processor X6800 and
Intel
®
Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
Due to this erratum, a logical processor may not resume execution until the
next targeted interrupt event or O/S timer tick following a locked store that
spans across cache lines within the monitored address range.
Implication:
The logical processor that executed the MWAIT instruction may not resume
execution until the next targeted interrupt event or O/S timer tick in the case
where the monitored address is written by a locked store which is split across
cache lines.
Workaround:
Do not use locked stores that span cache lines in the monitored address
range.
Status:
For the steppings affected, see the Summary Tables of Changes.
AI37.
REP CMPS/SCAS Operations May Terminate Early in 64-bit Mode
when RCX >= 0X100000000
Problem:
REP CMPS (Compare String) and SCAS (Scan String) instructions in 64-bit
mode may terminate before the count in RCX reaches zero if the initial value
of RCX is greater than or equal to 0X100000000.
Implication:
Early termination of REP CMPS/SCAS operation may be observed and RFLAGS
may be incorrectly updated.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AI38.
FXSAVE/FXRSTOR Instructions which Store to the End of the
Segment and Cause a Wrap to a Misaligned Base Address (Alignment
<= 0x10h) May Cause FPU Instruction or Operand Pointer Corruption
Problem:
If a FXSAVE/FXRSTOR instruction stores to the end of the segment causing a
wrap to a misaligned base address (alignment <= 0x10h), and one of the
following conditions is satisfied:
1)
32-bit addressing, obtained by using address-size override, when in 64-bit mode
2)
16-bit addressing in legacy or compatibility mode
Then, depending on the wrap-around point, one of the below saved values may be
corrupted:
•
FPU Instruction Pointer Offset
•
FPU Instruction Pointer Selector
•
FPU Operand Pointer Selector
•
FPU Operand Pointer Offset
Implication:
This erratum could cause FPU Instruction or Operand pointer corruption and
may lead to unexpected operations in the floating point exception handler.
Workaround:
Avoid segment base mis-alignment and address wrap-around at the segment
boundary.
Status:
For the steppings affected, see the Summary Tables of Changes.