Intel E6600 Specification Update - Page 37

Cache Data Access Request from One Core Hitting a Modified Line

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Errata AI39. Cache Data Access Request from One Core Hitting a Modified Line in the L1 Data Cache of the Other Core May Cause Unpredictable System Behavior Problem: When request for data from Core 1 results in a L1 cache miss, the request is sent to the L2 cache. If this request hits a modified line in the L1 data cache of Core 2, certain internal conditions may cause incorrect data to be returned to the Core 1. Implication: This erratum may cause unpredictable system behavior. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AI40. PREFETCHh Instruction Execution under Some Conditions May Lead to Processor Livelock Problem: PREFETCHh instruction execution after a split load and dependent upon ongoing store operations may lead to processor livelock. Implication: Due to this erratum, the processor may livelock. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AI41. PREFETCHh Instructions May Not be Executed when Alignment Check (AC) is Enabled Problem: PREFETCHT0, PREFETCHT1, PREFETCHT2 and PREFETCHNTA instructions may not be executed when Alignment Check is enabled. Implication: PREFETCHh instructions may not perform the data prefetch if Alignment Check is enabled. Workaround: Clear the AC flag (bit 18) in the EFLAGS register and/or the AM bit (bit 18) of Control Register CR0 to disable alignment checking. Status: For the steppings affected, see the Summary Tables of Changes. AI42. Upper 32 Bits of the FPU Data (Operand) Pointer in the FXSAVE Memory Image May Be Unexpectedly All 1's after FXSAVE Problem: The upper 32 bits of the FPU Data (Operand) Pointer may incorrectly be set to all 1's instead of the expected value of all 0's in the FXSAVE memory image if all of the following conditions are true: • The processor is in 64-bit mode. • The last floating point operation was in compatibility mode • Bit 31 of the FPU Data (Operand) Pointer is set. • An FXSAVE instruction is executed Implication: Software depending on the full FPU Data (Operand) Pointer may behave unpredictably. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 37 Specification Update

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Errata
Intel
®
Core™2 Extreme Processor X6800 and
Intel
®
Core™2 Duo Desktop Processor E6000 and E4000 Sequence
37
Specification Update
AI39.
Cache Data Access Request from One Core Hitting a Modified Line in
the L1 Data Cache of the Other Core May Cause Unpredictable System
Behavior
Problem:
When request for data from Core 1 results in a L1 cache miss, the request is
sent to the L2 cache. If this request hits a modified line in the L1 data cache
of Core 2, certain internal conditions may cause incorrect data to be returned
to the Core 1.
Implication:
This erratum may cause unpredictable system behavior.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AI40.
PREFETCHh Instruction Execution under Some Conditions May Lead
to Processor Livelock
Problem:
PREFETCHh instruction execution after a split load and dependent upon
ongoing store operations may lead to processor livelock.
Implication:
Due to this erratum, the processor may livelock.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AI41.
PREFETCHh Instructions May Not be Executed when Alignment Check
(AC) is Enabled
Problem:
PREFETCHT0, PREFETCHT1, PREFETCHT2 and PREFETCHNTA instructions may
not be executed when Alignment Check is enabled.
Implication:
PREFETCHh instructions may not perform the data prefetch if Alignment
Check is enabled.
Workaround:
Clear the AC flag (bit 18) in the EFLAGS register and/or the AM bit (bit 18) of
Control Register CR0 to disable alignment checking.
Status:
For the steppings affected, see the Summary Tables of Changes.
AI42.
Upper 32 Bits of the FPU Data (Operand) Pointer in the FXSAVE
Memory Image May Be Unexpectedly All 1's after FXSAVE
Problem:
The upper 32 bits of the FPU Data (Operand) Pointer may incorrectly be set
to all 1's instead of the expected value of all 0's in the FXSAVE memory
image if all of the following conditions are true:
•
The processor is in 64-bit mode.
•
The last floating point operation was in compatibility mode
•
Bit 31 of the FPU Data (Operand) Pointer is set.
•
An FXSAVE instruction is executed
Implication:
Software depending on the full FPU Data (Operand) Pointer may behave
unpredictably.