Intel Pga478 Data Sheet - Page 33

Package Mechanical Specifications and Pin Information-Intel® Celeron® Processor 1.66 GHz/ 1.83 GHz Table 11. Signal Description (Sheet 4 of 7) Name Type Description Data strobe used to latch in D[63:0]#. DSTBN[3:0]# Input/ Output Signals D[15:0]#, DINV[0]# D[31:16]#, DINV[1]# D[47:32]#, DINV[2]# D[63:48]#, DINV[3]# Associated Strobe DSTBN[0]# DSTBN[1]# DSTBN[2]# DSTBN[3]# DSTBP[3:0]# Input/ Output Data strobe used to latch in D[63:0]#. Signals D[15:0]#, DINV[0]# D[31:16]#, DINV[1]# D[47:32]#, DINV[2]# D[63:48]#, DINV[3]# Associated Strobe DSTBP[0]# DSTBP[1]# DSTBP[2]# DSTBP[3]# FERR#/PBE# FORCEPR# GTLREF HIT# HITM# IERR# Output Input Input Input/ Output Input/ Output Output FERR# (Floating-point Error) PBE# (Pending Break Event) is a multiplexed signal and its meaning is qualified with STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating point error when the processor detects an unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MSDOS*-type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state. When FERR#/PBE# is asserted, indicating a break event, it remains asserted until STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active also causes an FERR# break event. For additional information on the pending break event functionality, including identification of support of the feature and enable/disable information, refer to the Intel® 64 and IA-32 Architectures Software Developer's Manuals in Volume 3A/3B: System Programming Guide and the Intel® Processor Identification and CPUID Instruction application note (AP-485) application note. The FORCEPR# input can be used by the platform to force the Intel® Celeron® Processor 1.66 GHz/1.83 GHz system bus to activate the Thermal Control Circuit (TCC). The TCC remains active until the system deasserts FORCEPR#. GTLREF determines the signal reference level for AGTL+ input pins. GTLREF should be set at 2/3* VCCP. GTLREF is used by the AGTL+ receivers to determine if a signal is a logical 0 or logical 1. HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Either FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor keeps IERR# asserted until the assertion of RESET#, BINIT#, or INIT#. January 2007 Order Number: 315876-002 Intel® Celeron® Processor 1.66 GHz/1.83 GHz DS 33