Intel SL6VU Specification Update - Page 11

Summary Tables of Changes R NO. E0 nC1 nD1 AC28 X AC29 X AC30 X X X AC31 X X X AC32 X X X AC33 X AC34 X X X AC35 X AC36 X AC37 X X X AC38 S X X X AC39 X AC40 X X X AC41 X AC42 X X AC43 X AC44 X X AC45 X X AC46 X X X AC47 X X X AC48 X X X Plans ERRATA Fixed Fixed NoFix NoFix NoFix Fixed NoFix Fixed Fixed NoFix NoFix Fixed NoFix Fixed NoFix Fixed Fixed Multiple accesses to the same S-state L2 cache line and ECC error combination may result in loss of cache coherency Processor may hang when resuming from Deep Sleep state When the processor is in the System Management Mode (SMM), debug registers may be fully writeable Associated counting logic must be configured when using Event Selection Control (ESCR) MSR IA32_MC0_ADDR and IA32_MC0_MISC registers will contain invalid or stale data following a Data, Address, or Response Parity Error CR2 may be incorrect or an incorrect page fault error code may be pushed onto stack after execution of an LSS instruction System may hang if a fatal cache error causes Bus Write Line (BWL) transaction to occur to the same cache line address as an outstanding Bus Read Line (BRL) or Bus Read-Invalidate Line (BRIL) Processor Does not Flag #GP on Non-zero Write to Certain MSRs L2 cache may contain stale data in the Exclusive state Simultaneous assertion of A20M# and INIT# may result in incorrect data fetch Glitches on Address and Data Strobe Signals May Cause System Shutdown CPUID Returns Incorrect Number of ITLB Entries A Write to an APIC Register Sometimes May Appear to Have Not Occurred Store to Load Data Forwarding may Result in Switched Data Bytes Parity Error in the L1 Cache may Cause the Processor to Hang The TCK Input in the Test Access Port (TAP) is Sensitive to Low Clock Edge Rates and Prone to Noise Coupling Onto TCK's Rising or Falling Edges Re-mapping the APIC base address to a value less than or equal to 0xDC001000 may cause IO and Special Cycle failure Fixed Erroneous BIST result found in EAX register after reset NoFix NoFix NoFix The State of the Resume Flag (RF Flag) in a Task-State Segment (TSS) May be Incorrect Changes to CR3 Register do not Fence Pending Instruction Page Walks Processor Provides a 4-Byte Store Unlock After an 8-Byte Load Lock Intel® Celeron® Processor in the 478-Pin Package Specification Update 11