Intel SL6VU Specification Update - Page 47

Specification Clarifications R Specification Clarifications The Specification Clarifications listed in this section apply to the following documents: • Intel® Celeron® Processor in the 478-Pin Package Datasheet • Intel® 64 and IA-32 Intel® Architectures Software Developer's Manual, Volumes 1, 2-A, 2B, 3-A, and 3-B All Specification Clarifications will be incorporated into a future version of the appropriate Celeron processor documentation. 1. Specification Clarification with respect to Time Stamp Counter In the "Debugging and Performance Monitoring" chapter (Sections 15.8, 15.10.9 and 15.10.9.3) of the IA-32 Intel® Architecture Software Developer's Manual Volume 3: System Programming Guide, the Time Stamp Counter definition has been updated to include support for the future processors. This change will be incorporated in the next revision of the IA-32 Intel® Architecture Software Developer's Manual. 15.8 Time-Stamp Counter The IA-32 architecture (beginning with the Pentium processor) defines a time-stamp counter mechanism that can be used to monitor and identify the relative time occurrence of processor events. The counter's architecture includes the following components: • TSC flag - A feature bit that indicates the availability of the time-stamp counter. The counter is available in an IA-32 processor implementation if the function CPUID.1:EDX.TSC[bit 4] = 1. • IA32_TIME_STAMP_COUNTER MSR (called TSC MSR in P6 family and Pentium processors) - The MSR used as the counter. • RDTSC instruction - An instruction used to read the time-stamp counter. • TSD flag - A control register flag is used to enable or disable the time-stamp counter (enabled if CR4.TSD[bit 2] = 1). The time-stamp counter (as implemented in the P6 family, Pentium, Pentium M, Pentium 4, and Intel Xeon processors) is a 64-bit counter that is set to 0 following a RESET of the processor. Following a RESET, the counter will increment even when the processor is halted by the HLT instruction or the external STPCLK# pin. Note that the assertion of the external DPSLP# pin may cause the time-stamp counter to stop. Members of the processor families increment the time-stamp counter differently: • For Pentium M processors (family [06H], models [09H, 0DH]); for Pentium 4 processors, Intel Xeon processors (family [0FH], models [00H, 01H, or 02H]); and for P6 family processors: the time-stamp counter increments with every internal processor clock cycle. The Intel® Celeron® Processor in the 478-Pin Package Specification Update 47