Intel SL6VU Specification Update - Page 30

Errata R AC27. Processor Issues Inconsistent Transaction Size Attributes for Locked Operation Problem: When the processor is in the Page Address Extension (PAE) mode and detects the need to set the Access and/or Dirty bits in the page directory or page table entries, the processor sends an 8-byte load lock onto the system bus. A subsequent 8-byte store unlock is expected, but instead a 4-byte store unlock occurs. Correct data is provided since only the lower bytes change, however external logic monitoring the data transfer may be expecting an 8-byte store unlock. Implication: No known commercially available chipsets are affected by this erratum. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AC28. Multiple Accesses to the Same S-State L2 Cache Line and ECC Error Combination May Result in Loss of Cache Coherency Problem: When a Read for Ownership (RFO) cycle has a 64-bit address match with an outstanding read hit on a line in the L2 cache which is in the S-state AND that line contains an ECC error, the processor should recycle the RFO until the ECC error is handled. Due to this erratum, the processor does not recycle the RFO and attempts to service both the RFO and the read hit at the same time. Implication: When this erratum occurs, cache may become incoherent. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AC29. Processor May Hang When Resuming from Deep Sleep State Problem: When resuming from the Deep Sleep state the address strobe signals (ADSTB[1:0]#) may become out of phase with respect to the system bus clock (BCLK). Implication: When this erratum occurs, the processor will hang. Workaround: The system BIOS should prevent the processor from going to the Deep Sleep state. Status: For the steppings affected, see the Summary Tables of Changes. 30 Intel® Celeron® Processor in the 478-Pin Package Specification Update