LG 42LB1DRA Service Manual - Page 18

VIDEO TROUBLESHOOTING & BLOCK DIAGRAM DDR 32Mb - 18 - • DCR DVR ANT. Cabl e IIC 1 • Block Box-show the U-Com 0XC0 OOB IF+/- OOB/POD Contro ller (USA Only) IN/OUT connections ATSC/NTSC/ 2nd IF r(6M) VSB DATA POD_TP[0:7] OOB Tun er IF_AGC RF SW SIF M_MSP S_MSP 4440 4458G IIC 1 0XC2 SIF AT/NTSC Tune r Vid eo In/ Out 2nd IF r(6M) IF_AGC VV LGDT3703 Main X-tal IIC 3 11 DRX2/ CRXPI_CLKB DRX / CRX OOB_EN1_2 LGDT3502 POD/OOB Control ler (25M) 0x1C 8 74LCX244 PO 14 Ad d. [0:13] 8 PI D DRX / CRX PI_CLK LGDT3703 X-tal IIC 2 (25M) 0xB2 MUX CPLD V/Q _TP IIC 2 0xB8 POD CLK,V ALID,SOP 11 VPP_SW VPP_SW 8 Flag 2 Voltage Contr oller LTC1470 VPP1 VPP PC_TPOU TI PC_TPOUT2 MUX CPLD CP_TPN2[0:7] CP_TPN1[0:7] PVRsoc (LGDT1303) 1394_OUT_TP[0:7] 1394_IN_TP[0:7] 1394 Controll er 4 (TPA r,TPB r) *2 (TSB43DA42) 4 X-tal PCI Bus (25M) SATA I/F TX/RX P1,N1 HD2_NT2CLK (SiI3512) TX/RX P2,N2 PVR_SYS_CLK SDRAM 32MByte (8MB x4) EPLD_CLK CY2305SC VCXO LGDPLL IIC3 0x12 (LGDT1901B) HD2_TP[0:7] Rear AV_1 Rear S_1 EPF_L/R V, LR 3 YC 2 HD-II HD2_CVBS_OUT Side AV_2 V,LR 3 Side S_2 YC 2 MNT_V_Out IN1 TV IN5 2 IN1 OUT2 IN3 (Sub) A/V SW IN6 (CXA2069) IN4 OUT1 2 (Main) IN4 OUT3 M_MSP 4440 AV_L/R_OUT LR 2 OUT1 IIC 4 0x90 Comp_ 1 Comp_ 2 RGB-PC YCbCr 3 YCbCr 3 RGBHV 5 IN4 IIC 4 0x84 IN3 Video SW (CXA2181) IN2 IN1 Filter(opt) (FMS6410) 2 X-tal SDRAM 656 Data[ 0:7] (24.576M) (1Mx 16Bit) MUX Video Dec oder CPLD (UPD64015) 8 TP/D1 CP_656[0-7] CP_656_CLK 1.8V Reg. 27Mh 64-Bit I/F z HD2_MAIN_PWM HD-2.4 Filter(opt) (FMS6410) IIC 3 2 IIC 2 0xBA X-tal PDR 656[0:7] 656CLK SYS CPLD Sub SEL MSP4458G EXT_IN_CLK SUB_656_CLK SDRAM CY2309 -TP De-Mux - MPEG Decodi ng : MP@HL -Form at Co nverter 0x50 uCom MTV416 P_SW_2 (24.576M) (1Mx 16Bit) YCbCr Video Dec oder (UPD64015) 20H,V 2 CLK FID 30 OR1 30 YCbCr OR3 CPLD H,V OR2 FID YCbCr OR1 -Host I/F , Memo ry I/F -Digital I/F -NTSC Encod er -AC-3 Decod er/SPDIF In/out -IEP2 YCbCr 3 LPF(OPT) (FMS6403) ADC (MST3361) CLK H,V 2 FID OR3 CPLD AH_SPDIFCLK OR2 VBI Slicer & IR (USA Only) HD2_SYS_CLK HD2_VDPClk (74.25M) DPLL_R[1:3] HD2_REC_CVBS CXA2069 IIC2 XDR_DATA_R/G/B[0:9] 0x1E IEP3 HV,Hact 3 RGB 30DOutClk LVDS Tx. (THC63LVD103) TX[0:4]± TXC± 12 HD2_ICE958_OUT SPDIF SPDIF_IN_BYPASS H,V EPF_RGB-PC 5 RGBHV H,V AT/NT Tuner Rear L/R IIC 4 74LCX14 Syst em CPLD 2 FID 0x88 Sub I2S PVRSoc HV_PC OR2 Side L/R MSP HV_pol 4458G AT/NT_M_Tuner CXA2069 LR 2 MNT_Out LR AT/NT_S_Tune LLPPF SIF r I2S F I2S_MCLK 2 IIC 4 0x6C PWM MODULATOR PWM_L/R 2 (NSP2100A) Comp_ 1 LR IIC 4 ANALOG_L/R Comp_ 2 2 LR 0x80 Main 2 RGB(Phone) 2 LR Sound Proc (MSP4440) BUFFER (MC33078) I2S Out AUDIO ADC (CS5331) I2S In 3 3 GS_Y_2069 IIC 2 0x9C GS_V_TU MAIN_CVBS Volt age Comp. (LM311M) PWM AMP (TAS5122) PWM AMP (TAS5122) SYNC SEPARATOR H,V (MM1108XF) ANAL OG DE/ MULTIPL EXER (74HCT4053) GS_Y_1 U-COM (PIC18F1220) PIC18F242 UART1_RX/TX CPU GEM_IR_OUT EEPROM (AT24LC512) IIC 1 0xA6 Syst em CPLD HD2_DAC_SCK/LRCK Contro l GPIO Periph eral B us SPDIF Recei ver. (CS8415A) VCXO 33.33Mhz PCI Bus HDMI_SPDIF CY2309SC MST33611_HDMI CPU_CLK PCI_CLK_PVR PCI_CLK_1394 PCI_CLK_SATA RS-232C (ST3232) HD-2.4 IIC 1 G_LINK_CONN EN[0:3(GPIO)] CPU [PPC 405GPr] SDRAM 32Bit B us I/F 64MB(32MBx2) RXD[0:2]±, RXCLK ± 8 DDC(I2C) 2 RXD[0:2]±, RXCLK ± EEEEPPRROOMM 8 DDC(I2C) BBSSSS8833 HDMI Rx MST3361 IIC 2 RGB OR1 30 DE HD2 OR 3 H,V,DE 3 SYS CPLD IIC 2 IIC 3 IIC 4 I2C Hub (PCA9516) - SDRAM Controller - Peripheral Controller - Local BUS I/F - Serial(2), GPIO, I2Cr Reset KIA7029 74LCX244 Periph eral B us Flash Memory 16MB(8MBx2) EEEEPPRROOMM BBSSSS8833 0x9C CLK RESET CY2309