MSI B75MA User Guide - Page 30

DeTermines THe Timing of THe TransiTion from RAS row address sTrobe To CAS

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tCL Controls CAS latency which determines the timing delay (in clock cycles) of starting a read command after receiving data. tRCD Determines the timing of the transition from RAS (row address strobe) to CAS (column address strobe). The less clock cycles, the faster the DRAM performance. tRP Controls number of cycles for RAS (row address strobe) to be allowed to precharge. If insufficient time is allowed for RAS to accumulate before DRAM refresh, the DRAM may fail to retain data. This item applies only when synchronous DRAM is installed in the system. tRAS Determines the time RAS (row address strobe) takes to read from and write to memory cell. tRFC This setting determines the time RFC takes to read from and write to a memory cell. tWR Determines minimum time interval between end of write data burst and the start of a pre-charge command. Allows sense amplifiers to restore data to cell. tWTR Determines minimum time interval between the end of write data burst and the start of a column-read command; allows I/O gating to overdrive sense amplifies before read command starts. tRRD Specifies the active-to-active delay of different banks. tRTP Time interval between a read and a precharge command. tFAW This item is used to set the tFAW (four activate window delay) timing. tWCL This item is used to set the tWCL (Write CAS Latency) timing. tCKE This item is used to set the Pulse Width for DRAM module. tRTL This item is used to set Round Trip Latency settings. Advanced Channel 1/ 2 Timing Configuration Press to enter the sub-menu. And you can set the advanced memory timing for each channel. 30

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30
TCL
ConTrols CAS laTencY wHicH deTermines THe Timing delaY (in clock cYcles) of
sTarTing a read command afTer receiving daTa.
TRCD
DeTermines THe Timing of THe TransiTion from RAS (row address sTrobe) To CAS
(column address sTrobe). tHe less clock cYcles, THe fasTer THe DRAM perfor-
mance.
TRP
ConTrols number of cYcles for RAS (row address sTrobe) To be allowed To pre-
cHarge. If insufficienT Time is allowed for RAS To accumulaTe before DRAM re-
fresH, THe DRAM maY fail To reTain daTa. tHis iTem applies onlY wHen sYncHro-
nous DRAM is insTalled
in THe sYsTem.
TRAS
DeTermines THe Time RAS (row address sTrobe) Takes To read from and wriTe
To memorY cell.
TRFC
tHis seTTing deTermines THe Time RFC Takes To read from and wriTe To a memorY
cell.
TWR
DeTermines minimum Time inTerval beTween end of wriTe daTa bursT and THe sTarT
of a pre-cHarge command. Allows sense amplifiers To resTore daTa To cell.
TWtR
DeTermines minimum Time inTerval beTween THe end of wriTe daTa bursT and THe
sTarT of a column-read command; allows I/O gaTing To overdrive sense amplifies
before read command sTarTs.
TRRD
Specifies THe acTive-To-acTive delaY of differenT banks.
TRtP
time inTerval beTween a read and a precHarge command.
TFAW
tHis iTem is used To seT THe TFAW (four acTivaTe window delaY) Timing.
TWCL
tHis iTem is used To seT THe TWCL (WriTe CAS LaTencY) Timing.
TCKE
tHis iTem is used To seT THe Pulse WidTH for DRAM module.
TRtL
tHis iTem is used To seT Round trip LaTencY seTTings.
Advanced CHannel ±/ 2 timing ConfiguraTion
Press <EnTer> To enTer THe sub-menu. And You can seT THe advanced memorY
Timing for eacH cHannel.