MSI G41M4 User Guide - Page 24

Is rEQUIrED TO gUArANTEE ThAT DATA IN ThE wrITE bUffErs cAN bE wrITTEN TO - f memory

Get MSI G41M4 PDF manuals and user guides View all MSI G41M4 manuals
Add to My Manuals
Save this manual to your list of manuals

Page 24 highlights

address strobe) to CAS (column address strobe). The less the clock cycles, the faster the DRAM performance. tRP When the DRAM Timing Mode sets to [Manual], the field is adjustable. This item controls the number of cycles for Row Address Strobe (RAS) to be allowed to precharge. If insufficient time is allowed for the RAS to accumulate its charge before DRAM refresh, refreshing may be incomplete and DRAM may fail to retain data. This item applies only when synchronous DRAM is installed in the system. tRAS When the DRAM Timing Mode sets to [Manual], the field is adjustable. This setting determines the time RAS takes to read from and write to a memory cell. tRTP When the DRAM Timing Mode sets to [Manual], the field is adjustable. Time interval between a read and a precharge command. tRFC When the DRAM Timing Mode sets to [Manual], the field is adjustable. This setting determines the time RFC takes to read from and write to a memory cell. tWR When the DRAM Timing Mode is set to [Manual], the field is adjustable. It specifies the amount of delay (in clock cycles) that must elapse after the completion of a valid write operation, before an active bank can be precharged. This delay is required to guarantee that data in the write buffers can be written to the memory cells before precharge occurs. tRRD When the DRAM Timing Mode sets to [Manual], the field is adjustable. Specifies the active-to-active delay of different banks. tWTR When the DRAM Timing Mode is set to [Manual], the field is adjustable. This item controls the Write Data In to Read Command Delay memory timing. This constitutes the minimum number of clock cycles that must occur between the last valid write operation and the next read command to the same internal bank of the DDR device. FSB/DRAM Ratio This item will allow you to adjust the ratio of FSB to memory. Adjusted DRAM Frequency (MHz) It shows the adjusted memory frequency. Read-only. Adjust PCI-E Frequency (MHz) This item allows you to adjust the PCI-E frequency. Auto Disable DRAM/PCI Frequency When set to [Enabled], the system will remove (turn off) clocks from empty DIMM and PCI slots to minimize the electromagnetic interference (EMI). 24

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
  • 119
  • 120
  • 121
  • 122
  • 123
  • 124
  • 125
  • 126
  • 127
  • 128
  • 129
  • 130
  • 131
  • 132
  • 133
  • 134
  • 135
  • 136
  • 137
  • 138
  • 139
  • 140
  • 141
  • 142
  • 143
  • 144
  • 145
  • 146
  • 147
  • 148
  • 149
  • 150
  • 151
  • 152
  • 153
24
ADDrEss sTrObE) TO CaS (cOlUmN ADDrEss sTrObE). thE lEss ThE clOck cYclEs, ThE
fAsTEr ThE dRaM pErfOrmANcE.
TRP
WhEN ThE dRaM tImINg MODE sETs TO [MANUAl], ThE fiElD Is ADjUsTAblE. thIs
ITEm cONTrOls ThE NUmbEr Of cYclEs fOr ROw aDDrEss STrObE (RaS) TO bE Al-
lOwED TO prEchArgE. if INsUfficIENT TImE Is AllOwED fOr ThE RaS TO AccUmUlATE ITs
chArgE bEfOrE dRaM rEfrEsh, rEfrEshINg mAY bE INcOmplETE AND dRaM mAY
fAIl TO rETAIN DATA. thIs ITEm ApplIEs ONlY whEN sYNchrONOUs dRaM Is INsTAllED
IN ThE sYsTEm.
TRaS
WhEN ThE dRaM tImINg MODE sETs TO [MANUAl], ThE fiElD Is ADjUsTAblE. thIs sET-
TINg DETErmINEs ThE TImE RaS TAkEs TO rEAD frOm AND wrITE TO A mEmOrY cEll.
TRtP
WhEN ThE dRaM tImINg MODE sETs TO [MANUAl], ThE fiElD Is ADjUsTAblE. tImE
INTErvAl bETwEEN A rEAD AND A prEchArgE cOmmAND.
TRFC
WhEN ThE dRaM tImINg MODE sETs TO [MANUAl], ThE fiElD Is ADjUsTAblE. thIs sET-
TINg DETErmINEs ThE TImE RFC TAkEs TO rEAD frOm AND wrITE TO A mEmOrY cEll.
TWR
WhEN ThE dRaM tImINg MODE Is sET TO [MANUAl], ThE fiElD Is ADjUsTAblE. iT spEcI-
fiEs ThE AmOUNT Of DElAY (IN clOck cYclEs) ThAT mUsT ElApsE AfTEr ThE cOmplETION
Of A vAlID wrITE OpErATION, bEfOrE AN AcTIvE bANk cAN bE prEchArgED. thIs DElAY
Is rEQUIrED TO gUArANTEE ThAT DATA IN ThE wrITE bUffErs cAN bE wrITTEN TO ThE
mEmOrY cElls bEfOrE prEchArgE OccUrs.
TRRd
WhEN ThE dRaM tImINg MODE sETs TO [MANUAl], ThE fiElD Is ADjUsTAblE. SpEcI-
fiEs ThE AcTIvE-TO-AcTIvE DElAY Of DIffErENT bANks.
TWtR
WhEN ThE dRaM tImINg MODE Is sET TO [MANUAl], ThE fiElD Is ADjUsTAblE. thIs
ITEm cONTrOls ThE WrITE dATA iN TO READ COmmAND dElAY mEmOrY TImINg. thIs
cONsTITUTEs ThE mINImUm NUmbEr Of clOck cYclEs ThAT mUsT OccUr bETwEEN ThE
lAsT vAlID wrITE OpErATION AND ThE NExT rEAD cOmmAND TO ThE sAmE INTErNAl bANk
Of ThE ddR DEvIcE.
FSB/dRaM RATIO
thIs ITEm wIll AllOw YOU TO ADjUsT ThE rATIO Of FSB TO mEmOrY.
aDjUsTED dRaM FrEQUENcY (MHz)
iT shOws ThE ADjUsTED mEmOrY frEQUENcY. READ-ONlY.
aDjUsT PCi-e FrEQUENcY (MHz)
thIs ITEm AllOws YOU TO ADjUsT ThE PCi-e frEQUENcY.
aUTO dIsAblE dRaM/PCi FrEQUENcY
WhEN sET TO [eNAblED], ThE sYsTEm wIll rEmOvE (TUrN Off) clOcks frOm EmpTY diMM
AND PCi slOTs TO mINImIzE ThE ElEcTrOmAgNETIc INTErfErENcE (eMi).