MSI K9N2GM User Guide - Page 54

MS-7508 Mainboard, Adjust CPU FSB Frequency MHz, Adjust CPU Ratio, Advance DRAM Configuration, DRAM

Page 54 highlights

MS-7508 Mainboard Adjust CPU FSB Frequency (M Hz) This item allows you to select the CPU Front Side Bus clock frequency (in MHz). Adjust CPU Ratio This item is used to adjust CPU clock multiplier (ratio). It is available only when the processor supports this function. Advance DRAM Configuration Press to enter the sub-menu and the following screen appears. DRAM Timing Mode This field has the capacity to automatically detect all of the DRAM timing. If you set this field to [Manual], some fields will appear and selectable. tRC W hen the DRAM Timing M ode sets to [Manual], the field is adjustable. The rowcycle time determines the minimum number of clock cycles a memory row takes to complete a full cycle, from row activation up to the precharging of the ac t i ver ow . tRRD W hen the DRAM Timing Mode sets to [Manual], the field is adjustable. Specifies the active-to-active delay of different banks. Time interval between a read and a precharge command. tRCD W hen the DRAM Timing Mode sets to [Manual], the field is adjustable. W hen DRAM is refreshed, both rows and columns are addressed separately. This setup item allows you to determine the timing of the transition from RAS (row address strobe) to CAS (column address strobe). The less the clock cycles, the faster the DRAM performance. CAS# Latency (CL) W hen the DRAM Timing Mode sets to [Manual], the field is adjustable. This controls the CAS latency, which determines the timing delay (in clock cycles) before SDRAM starts a read command after receiving it. 3-20

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3-20
MS-7508 Mainboard
Adjust CPU FSB Frequency (MHz)
This item allows you to select the CPU Front Side Bus clock frequency (in MHz).
Adjust CPU Ratio
This item is used to adjust CPU clock multiplier (ratio). It is available only when the
processor supports this function.
Advance DRAM Configuration
Press <Enter> to enter the sub-menu and the following screen appears.
DRAM Timing Mode
This field has the capacity to automatically detect all of the DRAM timing. If you
set this field to [Manual], some fields will appear and selectable.
tRC
When the
DRAM Timing Mode
sets to [Manual], the field is adjustable. The
rowcycle time determines the minimum number of clock cycles a memory row
takes to complete a full cycle, from row activation up to the precharging of the
activerow.
tRRD
When the
DRAM Timing Mode
sets to [Manual], the field is adjustable. Speci-
fies the active-to-active delay of different banks. Time interval between a read
and a precharge command.
tRCD
When the
DRAM Timing Mode
sets to [Manual], the field is adjustable. When
DRAM is refreshed, both rows and columns are addressed separately. This
setup item allows you to determine the timing of the transition from RAS (row
address strobe) to CAS (column address strobe). The less the clock cycles, the
faster the DRAM performance.
CAS# Latency (CL)
When the
DRAM Timing Mode
sets to [Manual], the field is adjustable. This
controls the CAS latency, which determines the timing delay (in clock cycles)
before SDRAM starts a read command after receiving it.