Panasonic BT-4LH310 Parts List - Page 72

ML_Lane 1 p, Hot Plug Detect

Page 72 highlights

A B C D E F G H I J K L M N O P 1 2 3 4 5 6 7 8 9 10 FL3800 +1R2V_D_1 IC3802 C1AB00004118 C3818 0.1u 16V C3815 0.1u 16V C3816 0.1u 16V C3817 0.1u 16V C3814 0.1u 16V R3894 10k - IC3808 C0DBAYY00826 +3R3V_PVDD21_DP2 19:P3 DP2_HOTPLUG 1 3 IN OUT 2 C12 PVDD1 E7 PVDD1 E8 PVDD1 7 L1 1 LX 2 VSS 3 VOUT Thermal Pad 8 L2 6 VIN 5 VSS 4 CE/MODE C3844 4.7u 6.3V R3897 0 +5V_D L3805 J0JJC0000022 L3801 J0JJC0000022 L3802 J0JJC0000022 DGND R3800 4.7k C3810 16V 0.1u R3804 4.7k C3812 16V 0.1u R3808 4.7k R3801 4.7k C3800 1u 16V 0.1u 16V C3809 1 E0 DGND 8 VCC 2 E1 IP3800 C3EBDC000067 7 WC 85 VCC A 7 1 6 VEE GND INH 432 15:P4 SCL_VIN3 DGND +3R3V_D_3 DGND FL3801 +3R3V_PVDD21_DP2 1 3 IN OUT 2 DGND K6 PVDD1 K9 PVDD1 F10 PVDD21 F5 PVDD22 A14 PVSS3 C4 PVSS3 C14 PVSS3 F6 PVSS3 F7 PVSS3 F8 PVSS3 F9 PVSS3 C3820 0.1u 16V 0.1u C3822 16V C3843 10u 6.3V L3806 J0JJC0000022 CN3800 K1FY120E0006 CL3800 1M 100k G G 20 DP_PWR 19 Return 18 Hot Plug Detect 17 AUX CH (n) 16 GND 15 AUX CH (p) 14 CONFIG2 13 CONFIG1 12 ML_Lane 0 (p) 11 GND 10 ML_Lane 0 (n) 9 ML_Lane 1 (p) 8 GND 7 ML_Lane 1 (n) 6 ML_Lane 2 (p) 5 GND 4 ML_Lane 2 (n) 3 ML_Lane 3 (p) 2 GND 1 ML_Lane 3(n) R3853 1M R3854 1M R3862 R384-1 G 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 DGND G TP3800 DGND DGND +3R3V_PVDD21_DP2 G6 CABLE_DET_DP2 3 E2 4 VSS DGND 1M R3863 C3842 0.1u 16V 10k R3892 R3893 47 R3852 0 DGND VCC 5 1 4 INB OUTY 2 INA GND 3 DGND IC3807 C0JBAA000362 R3896 47 R3889 4.7k 4.7k R3856 6 SCL 5 SDA C3813 16V 0.1u DGND IC3804 C0JBAR000432 85 VCC A 7 1 6 VEE GND INH 432 DGND IC3805 C0JBAR000432 +3R3V_PVDD21_DP2 +30%-30% 10K 19:P3 DP2_EDID_CONF_P Q3801 47K DRC9114Y0L DGND +30%-30% 10K SDA_VIN3 1:E5/2:F7/3:F6/4:H3/15:P4 19:P3 DP2_EDID_CS_P 47K Q3802 DRC9114Y0L DGND DGND +1R2V_D_1 +1R2V_VDD_DP2_1 FL3803 F1H0J4740004 1 3 IN OUT 2 DGND C3832 0.1u 16V C3831 0.1u 16V C3830 0.1u 16V C3829 0.1u 16V AGND_DP2 +3R3V_D_3 L3804 J0JJC0000022 MPZ1608S300ATAH0 IC3806 C0DBGYY01486 1 5 VOUT VIN 2 FL3804 F1H0J4740004 AGND_DP2 1 3 IN OUT 2 G6 PVSS3 G7 PVSS3 G8 PVSS3 G9 PVSS3 H6 PVSS3 H7 PVSS3 H8 PVSS3 H9 PVSS3 J6 PVSS3 J7 PVSS3 J8 PVSS3 J9 PVSS3 B11 DPRX_VDDA_1V2 C7 DPRX_VDDA_1V2 C8 DPRX_VDDA_1V2 D9 DPRX_VDDA_1V2 D7 DPRX_VSSA D8 DPRX_VSSA E9 DPRX_VSSA E10 DPRX_VSSA C3837 0.1u 16V C3839 10u 6.3V VSS C3838 1u 16V 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k R3888 4.7k R3839 4.7k 4.7k R3838 D3812 D3810 D3809 D3808 D3807 D3806 D3805 D3804 D3803 D3811 EZAEG2A50AX DGND R3842 0 R3843 0 R3844 0 R3845 0 R3846 0 R3847 0 R3848 0 R3849 0 R3850 0 R3851 0 +1R2V_VDD_DP2_1 0.1u 16V C3805 AGND_DP2 +3R3V_AVDD_DP2 AGND_DP2 0.1u 16V C3806 1000p 50V C3836 R3807 R3809 R3810 R3891 R3813 R3814 IC3802 C1AB00004118 DGND B8 A8 B7 A7 C6 B6 D5 C5 C3807 C3808 0.1u 0.1u 16V 16V B9 C9 D10 C3801 7p R382-1 50V R3820 1.5k - 240 C10 A2 A3 R3818 1M D4 C3802 7p 50V R3819 0 X3800 H0J270500138 CL3818 G11 G12 C11 A13 B4 DPRX_ML_L0N IRQ/GPIO_25 DPRX_ML_L0P AUX_UART_RX/GPIO_24 DPRX_ML_L1N AUX_UART_TX/BOOT[7]/GPIO_23 DPRX_ML_L1P I2C_SDA/GPIO_22 DPRX_ML_L2N I2C_SCL/GPIO_21 DPRX_ML_L2P AUX_I2C_SDA/GPIO_16 DPRX_ML_L3N AUX_I2C_SCL/GPIO_15 DPRX_ML_L3P UART_RX/GPIO_14 DPRX_AUXN UART_TX/BOOT[6]/GPIO_13 DPRX_AUXP IR_IN/GPIO_12 DPRX_HPD_OUT/GPIO_26 CLK_OUT/GPIO_5 DPRX_REXT I2C_MST_SDA/GPIO_3 XTAL I2C_MST_SCL/GPIO_2 TCLK GPIO_1 VBUFC_RPLL GPIO_0 NC1 SPI_CSn/GPIO_17 NC2 SPI_CLK/GPIO_18 NC3 SPI_DO/GPIO_20 NC4 SPI_DI/GPIO_19 NC5 TESTMODE1 TESTMODE0 RESETn I2S_3/BOOT[5]/GPIO_11 I2S_2/BOOT[4]/GPIO_10 I2S_1/BOOT[3]/GPIO_9 I2S_0/BOOT[2]/GPIO_8 I2S_BCLK/BOOT[1]/GPIO_7 I2S_WCLK/BOOT[0]/GPIO_6 I2S_MCLK/GPIO_4 D12 11:F2/12:E10 A12 B12 D11 B13 CL3807 CL3806 3:N3/15:O7/15:P4 15:P4 B14 C13 E4 A1 G4 C1 F11 G10 C3 R3827 47 CL3805 CL3804 CL3803 CL3808 CL3814 CL3813 C4 E6 CL3801 F12 R3822 - 100 C8 E12 R3823 - 100 C8 E11 R3824 - 100 C8 D13 R3825 - 100 C8 G3 R3860 0 F3 R3861 0 E5 DGND E3 11:F2/12:E10 F4 R3816 11:F2/12:E10 G5 EXBN8V680JX 11:F2/12:E10 B1 11:F2/12:E10 C2 11:F2/12:E10 D3 11:F2/12:E10 D2 11:G1 IRQ_DP2 SDA_VIN1 SCL_VIN1 CABLE_DET_DP2 SPI_CSN_DP2 SPI_CLK_DP2 SPI_DO_DP2 SPI_DI_DP2 D_3M_DP2[1] D_3M_DP2[3] D_3M_DP2[2] D_3M_DP2[0] DP2_FS64 DP2_FS CLK_12M_DP2_FS256 CE DGND3 DGND +3R3V_D_3 FL3802 1 3 IN OUT 2 AGND_DP2 NC 4 AGND_DP2 AGND_DP2 DGND +3R3V_AVDD_DP2 C3827 16V 0.1u AGND_DP2 16V 0.1u 16V 16V C3821 0.1u 16V C3823 0.1u 16V C3824 0.1u 16V C3825 0.1u C3826 0.1u C3819 AGND_DP2 AGND_DP2 B2 VSS_RPLL B3 VDD_RPLL D6 VDDA_3V3 H3 AVDD_OUT_LVTX_33 H12 AVDD_OUT_LVTX_33 L8 AVDD_OUT_LVTX_33 N1 AVDD_OUT_LVTX_33 N14 AVDD_OUT_LVTX_33 L7 AVDD_LVTX_33 F2 AVSS_OUT_LVTX F13 AVSS_OUT_LVTX H5 AVSS_OUT_LVTX H10 AVSS_OUT_LVTX K8 AVSS_OUT_LVTX P1 AVSS_OUT_LVTX P14 AVSS_OUT_LVTX K7 AVSS_LVTX AGND_DP2 R3886 0 0 R3887 DGND AGND_DP2 E0_LVTX_CH5N E0_LVTX_CH5P O0_LVTX_CH0N O0_LVTX_CH0P O0_LVTX_CH1N O0_LVTX_CH1P O0_LVTX_CH2N O0_LVTX_CH2P O0_LVTX_CLKN O0_LVTX_CLKP E1_LVTX_CH5N E1_LVTX_CH5P O1_LVTX_CH0N O1_LVTX_CH0P O1_LVTX_CH1N O1_LVTX_CH1P O1_LVTX_CH2N O1_LVTX_CH2P O1_LVTX_CLKN O1_LVTX_CLKP E0_LVTX_CH6N E0_LVTX_CH6P O0_LVTX_CH3N O0_LVTX_CH3P E0_LVTX_CH0N E0_LVTX_CH0P E0_LVTX_CH1N E0_LVTX_CH1P E0_LVTX_CH2N E0_LVTX_CH2P E1_LVTX_CH6N E1_LVTX_CH6P O1_LVTX_CH3N O1_LVTX_CH3P E1_LVTX_CH0N E1_LVTX_CH0P E1_LVTX_CH1N E1_LVTX_CH1P E1_LVTX_CH2N E1_LVTX_CH2P O0_LVTX_CH5N O0_LVTX_CH5P E0_LVTX_CLKN E0_LVTX_CLKP E0_LVTX_CH3N E0_LVTX_CH3P O0_LVTX_CH4N O0_LVTX_CH4P E0_LVTX_CH4N E0_LVTX_CH4P O1_LVTX_CH5N O1_LVTX_CH5P E1_LVTX_CLKN E1_LVTX_CLKP E1_LVTX_CH3N E1_LVTX_CH3P O1_LVTX_CH4N O1_LVTX_CH4P E1_LVTX_CH4N E1_LVTX_CH4P O1_LVTX_CH6P O1_LVTX_CH6N O0_LVTX_CH6P O0_LVTX_CH6N L6 M7 N13 P13 N12 P12 M11 N11 L10 M10 H4 J5 G14 G13 H14 H13 J13 J12 K11 K12 L4 M3 M9 N9 N7 P7 M6 N6 L5 M5 K5 J4 L13 L12 M2 M1 L3 L2 K4 K3 L9 M8 M4 N4 N3 P3 N8 P8 N2 P2 H11 J10 J3 J2 H2 H1 M14 M13 G2 G1 K10 J11 L11 M12 +3R3V_PVDD21_DP2 R3817 EXBN8V680JX R3840 R3890 2.7k R3833 4.7k R3832 4.7k R3855 4.7k 4.7k G7 SPI_DO_DP2 G6 SPI_CLK_DP2 SPI_CSN_DP2 G6 SPI_DI_DP2 G7 CN3801 1 +3R3V VCC 2 DATA OUT 3 CLK 4 CHIP SELECT 5 DATA IN 6 GND 1 2 3 4 5 6 SMT STRAIGHT DGND +3R3V_PVDD21_DP2 D3813 DB2S31100L IP3801 C3FBKY000071 1S 2Q 3W 4 VSS DGND 8 VCC 7 HOLD 6 C 5 D R3829 4.7k R3828 4.7k DGND DGND 0.1u 16V C3804 0.1u 16V C3840 DGND R3831 R3830 R3835 R3834 R3837 R3836 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k C3841 100p 50V +30%-30% 10K 47 47K R3815 Q3803 DRC9114Y0L DGND DGND 19:P3 RESET_DP2 R3867 N2 N2 N3 N3 N3 N3 N3 N3 N3 N3 N4 N4 N4 N4 N4 N4 N4 N4 N4 N4 N6 N6 N5 N5 N5 N5 N5 N6 N5 N6 N6 N6 N7 N7 N7 N7 N7 N7 N7 N7 N8 N8 N8 N8 N8 N8 N8 N8 N8 N8 N9 N9 N9 N9 N9 N9 N10 N10 N10 N10 D_165M_DP2_1_RE[9] D_165M_DP2_1_RE[8] D_165M_DP2_1_RE[7] D_165M_DP2_1_RE[6] D_165M_DP2_1_RE[5] D_165M_DP2_1_RE[4] D_165M_DP2_1_RE[3] D_165M_DP2_1_RE[2] D_165M_DP2_1_RE[1] D_165M_DP2_1_RE[0] D_165M_DP2_1_RO[9] D_165M_DP2_1_RO[8] D_165M_DP2_1_RO[7] D_165M_DP2_1_RO[6] D_165M_DP2_1_RO[5] D_165M_DP2_1_RO[4] D_165M_DP2_1_RO[3] D_165M_DP2_1_RO[2] D_165M_DP2_1_RO[1] D_165M_DP2_1_RO[0] D_165M_DP2_1_GE[9] D_165M_DP2_1_GE[8] D_165M_DP2_1_GE[7] D_165M_DP2_1_GE[6] D_165M_DP2_1_GE[5] D_165M_DP2_1_GE[4] D_165M_DP2_1_GE[3] D_165M_DP2_1_GE[2] D_165M_DP2_1_GE[1] D_165M_DP2_1_GE[0] D_165M_DP2_1_GO[9] D_165M_DP2_1_GO[8] D_165M_DP2_1_GO[7] D_165M_DP2_1_GO[6] D_165M_DP2_1_GO[5] D_165M_DP2_1_GO[4] D_165M_DP2_1_GO[3] D_165M_DP2_1_GO[2] D_165M_DP2_1_GO[1] D_165M_DP2_1_GO[0] D_165M_DP2_1_BE[9] D_165M_DP2_1_BE[8] D_165M_DP2_1_BE[7] D_165M_DP2_1_BE[6] D_165M_DP2_1_BE[5] D_165M_DP2_1_BE[4] D_165M_DP2_1_BE[3] D_165M_DP2_1_BE[2] D_165M_DP2_1_BE[1] D_165M_DP2_1_BE[0] D_165M_DP2_1_BO[9] D_165M_DP2_1_BO[8] D_165M_DP2_1_BO[7] D_165M_DP2_1_BO[6] D_165M_DP2_1_BO[5] D_165M_DP2_1_BO[4] D_165M_DP2_1_BO[3] D_165M_DP2_1_BO[2] D_165M_DP2_1_BO[1] D_165M_DP2_1_BO[0] R3866 EXBN8V680JX 10:F2/10:G11 VS_DP2 10:F3/10:G11 DE_DP2 10:F2/10:G11 HS_DP2 10:G1 47 CLK_165M_DP2 L2 D_165M_DP2_1_RE[9] L2 D_165M_DP2_1_RE[8] L3 D_165M_DP2_1_RE[4] L3 D_165M_DP2_1_RE[5] L2 D_165M_DP2_1_RE[7] L3 D_165M_DP2_1_RE[6] L3 D_165M_DP2_1_RE[0] L3 D_165M_DP2_1_RE[1] L3 D_165M_DP2_1_RE[2] L3 D_165M_DP2_1_RE[3] D_165M_DP2_1_RO[9] L3 L3 D_165M_DP2_1_RO[8] L3 D_165M_DP2_1_RO[7] L3 D_165M_DP2_1_RO[6] L3 D_165M_DP2_1_RO[5] L4 D_165M_DP2_1_RO[4] L4 D_165M_DP2_1_RO[3] L4 D_165M_DP2_1_RO[2] L4 D_165M_DP2_1_RO[1] L4 D_165M_DP2_1_RO[0] L5 D_165M_DP2_1_GE[1] L4 D_165M_DP2_1_GE[3] L4 D_165M_DP2_1_GE[4] D_165M_DP2_1_GE[5] L4 L4 D_165M_DP2_1_GE[6] L4 D_165M_DP2_1_GE[7] L4 D_165M_DP2_1_GE[8] L4 D_165M_DP2_1_GE[9] L5 D_165M_DP2_1_GE[0] L4 D_165M_DP2_1_GE[2] D_165M_DP2_1_GO[8] L5 L5 D_165M_DP2_1_GO[9] D_165M_DP2_1_GO[4] L5 L5 D_165M_DP2_1_GO[7] D_165M_DP2_1_GO[6] L5 D_165M_DP2_1_GO[5] L5 L5 D_165M_DP2_1_GO[0] D_165M_DP2_1_GO[1] L5 L5 D_165M_DP2_1_GO[2] D_165M_DP2_1_GO[3] L5 L6 D_165M_DP2_1_BE[6] L6 D_165M_DP2_1_BE[7] L6 D_165M_DP2_1_BE[4] L6 D_165M_DP2_1_BE[5] L6 D_165M_DP2_1_BE[0] D_165M_DP2_1_BE[1] L6 L6 D_165M_DP2_1_BE[9] D_165M_DP2_1_BE[3] L6 D_165M_DP2_1_BE[2] L6 D_165M_DP2_1_BE[8] L6 L6 D_165M_DP2_1_BO[9] D_165M_DP2_1_BO[8] L6 D_165M_DP2_1_BO[7] L6 L7 D_165M_DP2_1_BO[6] L7 D_165M_DP2_1_BO[5] D_165M_DP2_1_BO[4] L7 D_165M_DP2_1_BO[3] L7 D_165M_DP2_1_BO[2] L7 D_165M_DP2_1_BO[1] L7 D_165M_DP2_1_BO[0] L7 R3885 EXBN8V680JX 10:F5/10:G11 10:F5/10:G11 10:F5/10:G11 10:F5/10:G11 10:F5/10:G10 10:F5/10:G10 10:F4/10:G10 10:F4/10:G10 10:F4/10:G10 10:F5/10:G10 R3884 EXBN8V680JX R3883 EXBN8V680JX R3882 EXBN8V680JX D_165M_DP2_RE[9] D_165M_DP2_RE[8] D_165M_DP2_RE[4] D_165M_DP2_RE[5] D_165M_DP2_RE[7] D_165M_DP2_RE[6] D_165M_DP2_RE[0] D_165M_DP2_RE[1] D_165M_DP2_RE[2] D_165M_DP2_RE[3] 10:E11/10:F8 10:E11/10:F7 10:E10/10:F7 10:E10/10:F7 10:E11/10:F7 10:E11/10:F7 10:E10/10:F7 10:E10/10:F7 10:E10/10:F7 10:E10/10:F7 R3881 EXBN8V680JX R3880 EXBN8V680JX R3879 EXBN8V680JX D_165M_DP2_RO[9] D_165M_DP2_RO[8] D_165M_DP2_RO[7] D_165M_DP2_RO[6] D_165M_DP2_RO[5] D_165M_DP2_RO[4] D_165M_DP2_RO[3] D_165M_DP2_RO[2] D_165M_DP2_RO[1] D_165M_DP2_RO[0] R3878 EXBN8V680JX R3877 EXBN8V680JX R3876 EXBN8V680JX 10:F3/10:G9 10:F3/10:G9 10:F3/10:G9 10:F3/10:G9 10:F3/10:G9 10:F3/10:G9 10:F3/10:G9 10:F3/10:G8 10:F3/10:G8 10:F3/10:G8 D_165M_DP2_GE[1] D_165M_DP2_GE[3] D_165M_DP2_GE[4] D_165M_DP2_GE[5] D_165M_DP2_GE[6] D_165M_DP2_GE[7] D_165M_DP2_GE[8] D_165M_DP2_GE[9] D_165M_DP2_GE[0] D_165M_DP2_GE[2] R3875 EXBN8V680JX R3874 EXBN8V680JX R3873 EXBN8V680JX 10:E9/10:F6 10:E9/10:F6 10:E9/10:F6 10:E9/10:F6 10:E9/10:F6 10:E9/10:F6 10:E8/10:F5 10:E8/10:F5 10:E8/10:F5 10:E9/10:F5 D_165M_DP2_GO[8] D_165M_DP2_GO[9] D_165M_DP2_GO[4] D_165M_DP2_GO[7] D_165M_DP2_GO[6] D_165M_DP2_GO[5] D_165M_DP2_GO[0] D_165M_DP2_GO[1] D_165M_DP2_GO[2] D_165M_DP2_GO[3] 10:F4/10:G9 10:F4/10:G10 10:F4/10:G9 10:F4/10:G9 10:F4/10:G10 10:F4/10:G9 10:F4/10:G10 10:F4/10:G9 10:F4/10:G10 10:F4/10:G10 R3872 EXBN8V680JX R3871 EXBN8V680JX R3870 EXBN8V680JX D_165M_DP2_BE[6] D_165M_DP2_BE[7] D_165M_DP2_BE[4] D_165M_DP2_BE[5] D_165M_DP2_BE[0] D_165M_DP2_BE[1] D_165M_DP2_BE[9] D_165M_DP2_BE[3] D_165M_DP2_BE[2] D_165M_DP2_BE[8] 10:E10/10:F7 10:E10/10:F7 10:E9/10:F7 10:E9/10:F6 10:E10/10:F6 10:E9/10:F6 10:E9/10:F6 10:E9/10:F6 10:E10/10:F6 10:E10/10:F6 R3869 EXBN8V680JX R3868 EXBN8V680JX D_165M_DP2_BO[9] D_165M_DP2_BO[8] D_165M_DP2_BO[7] D_165M_DP2_BO[6] D_165M_DP2_BO[5] D_165M_DP2_BO[4] D_165M_DP2_BO[3] D_165M_DP2_BO[2] D_165M_DP2_BO[1] D_165M_DP2_BO[0] 11 Ref No.3800 3999 Series 12 CIRCUIT NAME LCD_MAIN (5/32) MODEL BT-4LH310 PAGE No. DIA - 9

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OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
Thermal Pad
G
G
G
G
STRAIGHT
SMT
C3804
0.1u
16V
C3816
0.1u
16V
C3820
0.1u
16V
C3832
0.1u
16V
C3830
0.1u
16V
C3817
0.1u
16V
C3819
0.1u
16V
C3829
0.1u
16V
C3814
0.1u
16V
C3824
0.1u
16V
C3822
0.1u
16V
C3818
0.1u
16V
C3831
0.1u
16V
C3827
0.1u
16V
C3826
0.1u
16V
C3815
0.1u
16V
C3821
0.1u
16V
C3823
0.1u
16V
C3800
1u
16V
C3806
0.1u
16V
C3813
0.1u
16V
C3812
0.1u
16V
C3807
0.1u
16V
C3810
0.1u
16V
C3808
0.1u
16V
C3801
7p
50V
C3805
0.1u
16V
C3825
0.1u
16V
C3809
0.1u
16V
C3802
7p
50V
C3837
0.1u
16V
C3839
10u
6.3V
C3840
0.1u
16V
C3838
1u
16V
C3836
1000p
50V
C3841
100p
50V
C3842
0.1u
16V
C3844
4.7u
6.3V
C3843
10u
6.3V
D3813
DB2S31100L
D3804
D3807
D3808
D3805
D3811
EZAEG2A50AX
D3803
D3812
D3806
D3809
D3810
FL3803
F1H0J4740004
1
2
3
FL3804
F1H0J4740004
1
2
3
FL3800
1
2
3
FL3801
1
2
3
FL3802
1
2
3
IC3807
C0JBAA000362
1
INB
2
INA
3
GND
4
OUTY
5
VCC
C1AB00004118
IC3802
B8
DPRX_ML_L0N
A8
DPRX_ML_L0P
B7
DPRX_ML_L1N
A7
DPRX_ML_L1P
C6
DPRX_ML_L2N
B6
DPRX_ML_L2P
D5
DPRX_ML_L3N
C5
DPRX_ML_L3P
B9
DPRX_AUXN
C9
DPRX_AUXP
D10
DPRX_HPD_OUT/GPIO_26
C10
DPRX_REXT
A2
XTAL
A3
TCLK
D4
VBUFC_RPLL
G11
NC1
G12
NC2
C11
NC3
A13
NC4
B4
NC5
D2
I2S_MCLK/GPIO_4
D3
I2S_WCLK/BOOT[0]/GPIO_6
C2
I2S_BCLK/BOOT[1]/GPIO_7
B1
I2S_0/BOOT[2]/GPIO_8
G5
I2S_1/BOOT[3]/GPIO_9
F4
I2S_2/BOOT[4]/GPIO_10
E3
I2S_3/BOOT[5]/GPIO_11
E5
RESETn
F3
TESTMODE0
G3
TESTMODE1
D13
SPI_DI/GPIO_19
E11
SPI_DO/GPIO_20
E12
SPI_CLK/GPIO_18
F12
SPI_CSn/GPIO_17
E6
GPIO_0
C3
GPIO_1
G10
I2C_MST_SCL/GPIO_2
F11
I2C_MST_SDA/GPIO_3
C1
CLK_OUT/GPIO_5
G4
IR_IN/GPIO_12
A1
UART_TX/BOOT[6]/GPIO_13
E4
UART_RX/GPIO_14
C13
AUX_I2C_SCL/GPIO_15
B14
AUX_I2C_SDA/GPIO_16
B13
I2C_SCL/GPIO_21
D11
I2C_SDA/GPIO_22
B12
AUX_UART_TX/BOOT[7]/GPIO_23
A12
AUX_UART_RX/GPIO_24
D12
IRQ/GPIO_25
C1AB00004118
IC3802
C12
PVDD1
E7
PVDD1
E8
PVDD1
K6
PVDD1
K9
PVDD1
F10
PVDD21
F5
PVDD22
A14
PVSS3
C4
PVSS3
C14
PVSS3
F6
PVSS3
F7
PVSS3
F8
PVSS3
F9
PVSS3
G6
PVSS3
G7
PVSS3
G8
PVSS3
G9
PVSS3
H6
PVSS3
H7
PVSS3
H8
PVSS3
H9
PVSS3
J6
PVSS3
J7
PVSS3
J8
PVSS3
J9
PVSS3
B11
DPRX_VDDA_1V2
C7
DPRX_VDDA_1V2
C8
DPRX_VDDA_1V2
D9
DPRX_VDDA_1V2
D7
DPRX_VSSA
D8
DPRX_VSSA
E9
DPRX_VSSA
E10
DPRX_VSSA
B2
VSS_RPLL
B3
VDD_RPLL
D6
VDDA_3V3
H3
AVDD_OUT_LVTX_33
H12
AVDD_OUT_LVTX_33
L8
AVDD_OUT_LVTX_33
N1
AVDD_OUT_LVTX_33
N14
AVDD_OUT_LVTX_33
L7
AVDD_LVTX_33
F2
AVSS_OUT_LVTX
F13
AVSS_OUT_LVTX
H5
AVSS_OUT_LVTX
H10
AVSS_OUT_LVTX
K8
AVSS_OUT_LVTX
P1
AVSS_OUT_LVTX
P14
AVSS_OUT_LVTX
K7
AVSS_LVTX
M12
O0_LVTX_CH6N
L11
O0_LVTX_CH6P
J11
O1_LVTX_CH6N
K10
O1_LVTX_CH6P
G1
E1_LVTX_CH4P
G2
E1_LVTX_CH4N
M13
O1_LVTX_CH4P
M14
O1_LVTX_CH4N
H1
E1_LVTX_CH3P
H2
E1_LVTX_CH3N
J2
E1_LVTX_CLKP
J3
E1_LVTX_CLKN
J10
O1_LVTX_CH5P
H11
O1_LVTX_CH5N
P2
E0_LVTX_CH4P
N2
E0_LVTX_CH4N
P8
O0_LVTX_CH4P
N8
O0_LVTX_CH4N
P3
E0_LVTX_CH3P
N3
E0_LVTX_CH3N
N4
E0_LVTX_CLKP
M4
E0_LVTX_CLKN
M8
O0_LVTX_CH5P
L9
O0_LVTX_CH5N
K3
E1_LVTX_CH2P
K4
E1_LVTX_CH2N
L2
E1_LVTX_CH1P
L3
E1_LVTX_CH1N
M1
E1_LVTX_CH0P
M2
E1_LVTX_CH0N
L12
O1_LVTX_CH3P
L13
O1_LVTX_CH3N
J4
E1_LVTX_CH6P
K5
E1_LVTX_CH6N
M5
E0_LVTX_CH2P
L5
E0_LVTX_CH2N
N6
E0_LVTX_CH1P
M6
E0_LVTX_CH1N
P7
E0_LVTX_CH0P
N7
E0_LVTX_CH0N
N9
O0_LVTX_CH3P
M9
O0_LVTX_CH3N
M3
E0_LVTX_CH6P
L4
E0_LVTX_CH6N
K12
O1_LVTX_CLKP
K11
O1_LVTX_CLKN
J12
O1_LVTX_CH2P
J13
O1_LVTX_CH2N
H13
O1_LVTX_CH1P
H14
O1_LVTX_CH1N
G13
O1_LVTX_CH0P
G14
O1_LVTX_CH0N
J5
E1_LVTX_CH5P
H4
E1_LVTX_CH5N
M10
O0_LVTX_CLKP
L10
O0_LVTX_CLKN
N11
O0_LVTX_CH2P
M11
O0_LVTX_CH2N
P12
O0_LVTX_CH1P
N12
O0_LVTX_CH1N
P13
O0_LVTX_CH0P
N13
O0_LVTX_CH0N
M7
E0_LVTX_CH5P
L6
E0_LVTX_CH5N
C0DBGYY01486
IC3806
1
VIN
2
VSS
3
CE
5
VOUT
4
NC
IP3800
C3EBDC000067
1
E0
2
E1
3
E2
4
VSS
5
SDA
6
SCL
7
WC
8
VCC
C3FBKY000071
IP3801
1
S
2
Q
3
W
4
VSS
5
D
6
C
7
HOLD
8
VCC
IC3808
C0DBAYY00826
1
LX
2
VSS
3
VOUT
4
CE/MODE
5
VSS
6
VIN
7
L1
8
L2
IC3804
C0JBAR000432
7
6
1
5
A
4
GND
VEE
3
8
VCC
2
INH
IC3805
C0JBAR000432
7
6
1
5
A
4
GND
VEE
3
8
VCC
2
INH
CN3800
K1FY120E0006
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CN3801
1
2
3
4
5
6
L3802
J0JJC0000022
L3805
J0JJC0000022
L3801
J0JJC0000022
L3804
J0JJC0000022
MPZ1608S300ATAH0
L3806
J0JJC0000022
+3R3V_PVDD21_DP2
+3R3V_AVDD_DP2
+1R2V_VDD_DP2_1
+3R3V_PVDD21_DP2
+3R3V_PVDD21_DP2
+3R3V_D_3
+3R3V_PVDD21_DP2
+3R3V_D_3
+1R2V_D_1
+5V_D
+3R3V_PVDD21_DP2
+3R3V_D_3
+1R2V_D_1
AGND_DP2
AGND_DP2
AGND_DP2
AGND_DP2
AGND_DP2
AGND_DP2
AGND_DP2
AGND_DP2
AGND_DP2
AGND_DP2
AGND_DP2
AGND_DP2
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
+3R3V_AVDD_DP2
+3R3V_PVDD21_DP2
+1R2V_VDD_DP2_1
TP3800
CL3801
CL3803
CL3813
CL3805
CL3806
CL3818
CL3800
CL3804
CL3808
CL3807
CL3814
D_165M_DP2_GE[7]
10:F3/10:G9
D_165M_DP2_BO[8]
10:E10/10:F7
D_165M_DP2_RO[9]
10:E11/10:F8
DP2_FS64
11:F2/12:E10
D_165M_DP2_RE[0]
10:F4/10:G10
D_165M_DP2_RO[2]
10:E10/10:F7
D_165M_DP2_GO[0]
10:E8/10:F5
D_165M_DP2_BE[4]
10:F4/10:G9
D_165M_DP2_GE[9]
10:F3/10:G8
D_165M_DP2_RO[3]
10:E10/10:F7
D_165M_DP2_BE[8]
10:F4/10:G10
D_165M_DP2_RO[4]
10:E11/10:F7
CLK_12M_DP2_FS256
11:G1
D_165M_DP2_BE[0]
10:F4/10:G10
D_165M_DP2_BO[3]
10:E9/10:F6
D_165M_DP2_RE[5]
10:F5/10:G11
D_165M_DP2_GO[2]
10:E8/10:F5
D_165M_DP2_BO[4]
10:E9/10:F6
D_3M_DP2[2]
11:F2/12:E10
D_165M_DP2_BE[7]
10:F4/10:G10
D_165M_DP2_RE[1]
10:F4/10:G10
D_165M_DP2_GE[2]
10:F3/10:G8
D_165M_DP2_RE[6]
10:F5/10:G10
D_165M_DP2_RE[4]
10:F5/10:G11
HS_DP2
10:F2/10:G11
D_165M_DP2_GE[1]
10:F3/10:G9
D_165M_DP2_GO[6]
10:E9/10:F6
D_165M_DP2_GE[0]
10:F3/10:G8
D_165M_DP2_GE[6]
10:F3/10:G9
D_165M_DP2_RE[3]
10:F5/10:G10
D_165M_DP2_RO[6]
10:E10/10:F7
D_165M_DP2_RO[8]
10:E11/10:F7
D_165M_DP2_GO[1]
10:E8/10:F5
D_165M_DP2_GO[7]
10:E9/10:F6
D_165M_DP2_RE[9]
10:F5/10:G11
D_165M_DP2_GO[4]
10:E9/10:F6
D_165M_DP2_RE[8]
10:F5/10:G11
D_165M_DP2_BO[7]
10:E9/10:F7
D_165M_DP2_BO[0]
10:E10/10:F6
D_165M_DP2_BO[9]
10:E10/10:F7
D_165M_DP2_GO[3]
10:E9/10:F5
D_165M_DP2_RO[7]
10:E10/10:F7
D_165M_DP2_RE[2]
10:F4/10:G10
IRQ_DP2
11:F2/12:E10
D_165M_DP2_BO[5]
10:E10/10:F6
D_165M_DP2_GE[8]
10:F3/10:G9
D_165M_DP2_BO[1]
10:E10/10:F6
D_165M_DP2_GE[3]
10:F3/10:G9
D_165M_DP2_RO[1]
10:E10/10:F7
D_165M_DP2_BE[2]
10:F4/10:G10
D_165M_DP2_BO[6]
10:E9/10:F6
D_165M_DP2_BE[6]
10:F4/10:G9
D_165M_DP2_BO[2]
10:E9/10:F6
D_165M_DP2_RE[7]
10:F5/10:G10
VS_DP2
10:F2/10:G11
D_165M_DP2_BE[1]
10:F4/10:G9
D_165M_DP2_BE[5]
10:F4/10:G9
CLK_165M_DP2
10:G1
D_165M_DP2_GO[9]
10:E9/10:F6
D_3M_DP2[1]
11:F2/12:E10
D_165M_DP2_GO[5]
10:E9/10:F6
D_3M_DP2[0]
11:F2/12:E10
D_165M_DP2_GO[8]
10:E9/10:F6
D_165M_DP2_BE[9]
10:F4/10:G10
DE_DP2
10:F3/10:G11
D_165M_DP2_RO[5]
10:E11/10:F7
D_165M_DP2_RO[0]
10:E10/10:F7
D_165M_DP2_GE[5]
10:F3/10:G9
D_165M_DP2_BE[3]
10:F4/10:G9
DP2_FS
11:F2/12:E10
D_165M_DP2_GE[4]
10:F3/10:G9
D_3M_DP2[3]
11:F2/12:E10
SDA_VIN1
3:N3/15:O7/15:P4
SDA_VIN3
1:E5/2:F7/3:F6/4:H3/15:P4
SCL_VIN1
15:P4
DP2_EDID_CONF_P
19:P3
RESET_DP2
19:P3
SCL_VIN3
15:P4
DP2_HOTPLUG
19:P3
DP2_EDID_CS_P
19:P3
D_165M_DP2_1_BO[1]
N10
D_165M_DP2_1_BO[6]
N9
D_165M_DP2_1_RO[2]
N4
SPI_DI_DP2
G7
D_165M_DP2_1_RE[0]
N3
D_165M_DP2_1_GE[7]
N5
D_165M_DP2_1_BE[2]
N8
D_165M_DP2_1_RO[4]
N4
D_165M_DP2_1_GO[5]
N7
D_165M_DP2_1_RE[7]
N3
D_165M_DP2_1_BE[3]
N8
D_165M_DP2_1_RE[2]
N3
D_165M_DP2_1_RO[7]
N4
D_165M_DP2_1_BE[8]
N8
D_165M_DP2_1_GO[9]
N6
D_165M_DP2_1_GE[0]
N6
SPI_CSN_DP2
C8
D_165M_DP2_1_GE[2]
N6
D_165M_DP2_1_RO[3]
N4
SPI_CLK_DP2
C8
D_165M_DP2_1_GO[6]
N7
D_165M_DP2_1_RE[6]
N3
D_165M_DP2_1_RO[5]
N4
D_165M_DP2_1_BE[6]
N8
D_165M_DP2_1_GO[8]
N6
D_165M_DP2_1_BE[9]
N8
D_165M_DP2_1_GE[4]
N5
D_165M_DP2_1_BO[0]
N10
D_165M_DP2_1_GO[4]
N7
D_165M_DP2_1_BO[9]
N9
D_165M_DP2_1_BO[5]
N9
D_165M_DP2_1_RE[3]
N3
D_165M_DP2_1_BE[5]
N8
D_165M_DP2_1_GE[5]
N5
D_165M_DP2_1_GO[7]
N7
D_165M_DP2_1_RE[9]
N2
D_165M_DP2_1_BO[4]
N9
D_165M_DP2_1_BE[7]
N8
D_165M_DP2_1_RO[0]
N4
D_165M_DP2_1_BO[7]
N9
D_165M_DP2_1_RO[6]
N4
D_165M_DP2_1_GO[3]
N7
D_165M_DP2_1_BO[3]
N10
D_165M_DP2_1_GO[2]
N7
D_165M_DP2_1_BO[8]
N9
D_165M_DP2_1_GE[6]
N5
D_165M_DP2_1_GO[1]
N7
D_165M_DP2_1_GE[1]
N5
CABLE_DET_DP2
G6
D_165M_DP2_1_GO[0]
N7
D_165M_DP2_1_RE[8]
N2
D_165M_DP2_1_RE[5]
N3
D_165M_DP2_1_BO[2]
N10
D_165M_DP2_1_BE[4]
N8
D_165M_DP2_1_GE[9]
N6
D_165M_DP2_1_RO[1]
N4
SPI_DO_DP2
C8
D_165M_DP2_1_BE[1]
N8
D_165M_DP2_1_GE[8]
N6
D_165M_DP2_1_GE[3]
N5
D_165M_DP2_1_RE[1]
N3
D_165M_DP2_1_BE[0]
N8
D_165M_DP2_1_RO[9]
N4
D_165M_DP2_1_RE[4]
N3
D_165M_DP2_1_RO[8]
N4
D_165M_DP2_1_GO[9]
L5
D_165M_DP2_1_RO[4]
L4
D_165M_DP2_1_BE[0]
L6
D_165M_DP2_1_BE[7]
L6
D_165M_DP2_1_RE[0]
L3
D_165M_DP2_1_BE[8]
L6
D_165M_DP2_1_BO[1]
L7
D_165M_DP2_1_BO[9]
L6
D_165M_DP2_1_BE[6]
L6
D_165M_DP2_1_BE[5]
L6
D_165M_DP2_1_BO[3]
L7
D_165M_DP2_1_BO[2]
L7
D_165M_DP2_1_GO[6]
L5
D_165M_DP2_1_BO[0]
L7
D_165M_DP2_1_GE[5]
L4
D_165M_DP2_1_RE[1]
L3
D_165M_DP2_1_RO[3]
L4
D_165M_DP2_1_RO[5]
L3
D_165M_DP2_1_RE[8]
L2
D_165M_DP2_1_BO[7]
L6
D_165M_DP2_1_GE[3]
L4
D_165M_DP2_1_RE[7]
L2
D_165M_DP2_1_GO[1]
L5
D_165M_DP2_1_GO[8]
L5
D_165M_DP2_1_BO[8]
L6
D_165M_DP2_1_RE[2]
L3
D_165M_DP2_1_RO[6]
L3
SPI_DO_DP2
G7
D_165M_DP2_1_RO[7]
L3
D_165M_DP2_1_GE[9]
L4
D_165M_DP2_1_GO[7]
L5
D_165M_DP2_1_RO[1]
L4
D_165M_DP2_1_GE[1]
L5
D_165M_DP2_1_BE[4]
L6
D_165M_DP2_1_RO[0]
L4
D_165M_DP2_1_RO[8]
L3
D_165M_DP2_1_RE[6]
L3
SPI_DI_DP2
C8
D_165M_DP2_1_GO[2]
L5
D_165M_DP2_1_GO[5]
L5
D_165M_DP2_1_RE[4]
L3
D_165M_DP2_1_RE[9]
L2
D_165M_DP2_1_RE[3]
L3
D_165M_DP2_1_BE[3]
L6
D_165M_DP2_1_GE[7]
L4
D_165M_DP2_1_BE[1]
L6
D_165M_DP2_1_GO[4]
L5
SPI_CSN_DP2
G6
SPI_CLK_DP2
G6
D_165M_DP2_1_GE[4]
L4
D_165M_DP2_1_GO[0]
L5
D_165M_DP2_1_GE[8]
L4
D_165M_DP2_1_RO[2]
L4
D_165M_DP2_1_BO[4]
L7
D_165M_DP2_1_BO[5]
L7
CABLE_DET_DP2
C4
D_165M_DP2_1_RO[9]
L3
D_165M_DP2_1_RE[5]
L3
D_165M_DP2_1_BO[6]
L7
D_165M_DP2_1_GE[2]
L4
D_165M_DP2_1_GE[0]
L5
D_165M_DP2_1_GE[6]
L4
D_165M_DP2_1_BE[9]
L6
D_165M_DP2_1_GO[3]
L5
D_165M_DP2_1_BE[2]
L6
Q3803
DRC9114Y0L
10K
47K
+30%-30%
Q3801
DRC9114Y0L
10K
47K
+30%-30%
Q3802
DRC9114Y0L
10K
47K
+30%-30%
R3870
EXBN8V680JX
R3868
EXBN8V680JX
R3884
EXBN8V680JX
R3881
EXBN8V680JX
R3875
EXBN8V680JX
R3877
EXBN8V680JX
R3882
EXBN8V680JX
R3876
EXBN8V680JX
R3878
EXBN8V680JX
R3874
EXBN8V680JX
R3885
EXBN8V680JX
R3866
EXBN8V680JX
R3817
EXBN8V680JX
R3869
EXBN8V680JX
R3816
EXBN8V680JX
R3880
EXBN8V680JX
R3883
EXBN8V680JX
R3879
EXBN8V680JX
R3873
EXBN8V680JX
R3872
EXBN8V680JX
R3871
EXBN8V680JX
R3814
4.7k
R3818
1M
R3844
0
R3848
0
R3810
4.7k
R3807
4.7k
R3829
4.7k
R3839
4.7k
R3854
1M
R3849
0
R3852
0
R3824
100
R3856
4.7k
R3887
0
R3886
0
R3833
4.7k
R3842
0
R3823
100
R3820
1.5k
R3841
100k
R3855
4.7k
R3851
0
R3801
4.7k
R3834
4.7k
R3828
4.7k
R3800
4.7k
R3843
0
R3819
0
R3830
4.7k
R3813
4.7k
R3808
4.7k
R3862
1M
R3809
4.7k
R3821
240
R3838
4.7k
R3888
4.7k
R3889
4.7k
R3890
2.7k
R3822
100
R3815
47
R3891
4.7k
R3832
4.7k
R3861
0
R3892
10k
R3837
4.7k
R3845
0
R3825
100
R3804
4.7k
R3893
47
R3860
0
R3846
0
R3836
4.7k
R3827
47
R3894
10k
R3863
1M
R3896
47
R3850
0
R3853
1M
R3897
0
R3867
47
R3847
0
R3831
4.7k
R3840
4.7k
R3835
4.7k
X3800
H0J270500138
Ref No.3800
3999 Series
20 DP_PWR
19 Return
18 Hot Plug Detect
17 AUX CH (n)
16 GND
15 AUX CH (p)
14 CONFIG2
13 CONFIG1
12 ML_Lane 0 (p)
11 GND
10 ML_Lane 0 (n)
9 ML_Lane 1 (p)
8 GND
7 ML_Lane 1 (n)
6 ML_Lane 2 (p)
5 GND
4 ML_Lane 2 (n)
3 ML_Lane 3 (p)
2 GND
1 ML_Lane 3(n)
1 +3R3V VCC
2 DATA OUT
3 CLK
4 CHIP SELECT
5 DATA IN
6 GND
-
-
-
-
-
-
-
-
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
1
2
3
4
5
6
7
8
9
10
11
12
CIRCUIT
NAME
MODEL
PAGE No.
DIA -
9
BT-4LH310
LCD_MAIN
(5/32)