Pioneer AVD-505 Service Manual - Page 27

Pin Functions LZ9GF16 - monitor

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AVD-505 - Pin Functions (LZ9GF16) Pin No. Pin Name I/O 1 VIN I 2 CVOP O 3 CVIN I 4 DVOP O 5 FRPT O 6 GPS O 7 GND 8 EXCL I/O 9 SYNI I 10 hsy I/O 11 vsy I/O 12 DIS O 13 TESTO O 14 NTPC I 15 VRVC I 16 HRVC I 17 CHK O 18 TESTI I 19 TESTO O 20 VR O 21 SPS O 22 CLS O 23 LOWO O 24 CTR O 25 SPD O 26 CLD O 27 OSCO O 28 OSCI I/O 29 SAMO O 30 VDD 31 GND 32 TESTI I 33 LOWI I 34 FRPV O 35 RESH I 36 PDP O 37 RESV I 38,39 TESTI I 40 IHR O 41 HR O 42 CLOC I 43 CLKC I 44 TESTI I 45 SAMC I 46 BLKI I 47 BLKO O 48 SYNO O Function and Operation Vertical synchronizing signal input (positive electrode) Vertical synchronizing countdown output Vertical synchronizing countdown input Digital separation vertically synchronized output (positive electrode) Signal output for common electrode drive signal polarity inversion Signal output for gate power supply Power supply ground Clock signal input/output Composite synchronizing signal input Horizontal synchronizing signal input/output (negative electrode) Vertical synchronizing signal input/output (negative electrode) Source driver control signal output Test monitor signal output Terminal for setting NTSC/PAL H:NTSC L:MBK-PAL Terminal for setting vertical scanning direction H:Normal L:Reverse Terminal for setting horizontal scanning direction H:Normal L:Reverse Control signal output for backlight PWM Light adjuster Input terminal for testing Test monitor signal output Vertical scanning direction setting output for gate driver Gate driver start signal output Gate driver clock signal output Gate driver control signal output Source driver control signal output Source driver start signal output Source driver clock signal output Clock oscillation circuit output Clock oscillation circuit input/output Source driver control signal output Power supply (+5V) Power supply ground Input terminal for testing Initial reset signal input Signal output for video signal polarity inversion Signal output reset terminal for source driver H:Normal L:Forced reset PLL Phase comparison circuit output Signal output reset terminal for gate driver H:Normal L:Forced reset Input terminal for testing Source driver control signal output Source driver control signal output Terminal for setting EXCL (clock signal) output H:L-Level output L:Clock output Terminal for setting clock · synchronizing signal input/output H:EXCL · hsy · vsy signal output L:EXCL · hsy · vsy signal input Input terminal for testing Terminal for setting sampling mode H:Non-simultaneous sampling L:Simultaneous sampling PLL phase comparison input Input BLKO delayed signal Output for PLL phase comparison signal Input into BLKI following delay Composite synchronizing signal output for vertical synchronized separation (positive electrode) 27

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27
AVD-505
-
Pin Functions (LZ9GF16)
Pin No.
Pin Name
I/O
Function and Operation
1
VIN
I
Vertical synchronizing signal input (positive electrode)
2
CVOP
O
Vertical synchronizing countdown output
3
CVIN
I
Vertical synchronizing countdown input
4
DVOP
O
Digital separation vertically synchronized output (positive electrode)
5
FRPT
O
Signal output for common electrode drive signal polarity inversion
6
GPS
O
Signal output for gate power supply
7
GND
Power supply ground
8
EXCL
I/O
Clock signal input/output
9
SYNI
I
Composite synchronizing signal input
10
hsy
I/O
Horizontal synchronizing signal input/output (negative electrode)
11
vsy
I/O
Vertical synchronizing signal input/output (negative electrode)
12
DIS
O
Source driver control signal output
13
TESTO
O
Test monitor signal output
14
NTPC
I
Terminal for setting NTSC/PAL
H:NTSC
L:MBK-PAL
15
VRVC
I
Terminal for setting vertical scanning direction
H:Normal
L:Reverse
16
HRVC
I
Terminal for setting horizontal scanning direction
H:Normal
L:Reverse
17
CHK
O
Control signal output for backlight PWM Light adjuster
18
TESTI
I
Input terminal for testing
19
TESTO
O
Test monitor signal output
20
VR
O
Vertical scanning direction setting output for gate driver
21
SPS
O
Gate driver start signal output
22
CLS
O
Gate driver clock signal output
23
LOWO
O
Gate driver control signal output
24
CTR
O
Source driver control signal output
25
SPD
O
Source driver start signal output
26
CLD
O
Source driver clock signal output
27
OSCO
O
Clock oscillation circuit output
28
OSCI
I/O
Clock oscillation circuit input/output
29
SAMO
O
Source driver control signal output
30
VDD
Power supply (+5V)
31
GND
Power supply ground
32
TESTI
I
Input terminal for testing
33
LOWI
I
Initial reset signal input
34
FRPV
O
Signal output for video signal polarity inversion
35
RESH
I
Signal output reset terminal for source driver
H:Normal
L:Forced reset
36
PDP
O
PLL Phase comparison circuit output
37
RESV
I
Signal output reset terminal for gate driver
H:Normal
L:Forced reset
38,39
TESTI
I
Input terminal for testing
40
IHR
O
Source driver control signal output
41
HR
O
Source driver control signal output
42
CLOC
I
Terminal for setting EXCL (clock signal) output
H:L-Level output
L:Clock output
43
CLKC
I
Terminal for setting clock · synchronizing signal input/output
H:EXCL ·
hsy
·
vsy
signal output
L:EXCL ·
hsy
·
vsy
signal input
44
TESTI
I
Input terminal for testing
45
SAMC
I
Terminal for setting sampling mode
H:Non-simultaneous sampling
L:Simultaneous sampling
46
BLKI
I
PLL phase comparison input
Input BLKO delayed signal
47
BLKO
O
Output for PLL phase comparison signal
Input into BLKI following delay
48
SYNO
O
Composite synchronizing signal output for vertical synchronized
separation (positive electrode)